* AM: add opt-in channel-power squelch for AM audio RX
Add an SDR++-style power squelch on the complex channel signal for the
Analog Audio RX app in AM modes (DSB/SSB/CW). The squelch measures the
mean channel power, converts it to dBFS, and mutes the demodulated audio
when the signal is below a user-set threshold. Being carrier-based it
keys on the AM carrier (e.g. airband/ATC) rather than on audio-band
noise, which the existing FM squelch could not do for AM.
A new 'SQ' field (0-99, 0 = off) is added to the AM options view and is
persisted per app via app_settings. Default is 0, so existing AM
behaviour is unchanged unless the user enables it. Threshold maps 1..99
to -80..-20 dBFS.
Touches: message (AMConfigureMessage.squelch_level), baseband_api
(AMConfig::apply), receiver_model (am_squelch_level get/set),
app_settings (persistence), proc_am_audio (DSP), analog_audio_app (UI).
* Refactor audio power calculation to use magnitude squared
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
---------
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
* Refactor app display to use scrollable menu
Removed specific app name text fields and replaced them with a scrollable menu for an unlimited app list.
* Refactor app display logic in ExternalModuleView
Refactor ExternalModuleView to manage app display more efficiently by using a menu instead of individual text fields.
* Update menu item color to use theme foreground color
* Ext Module: self-heal app list on transient read failures
Only skip rebuilding the scrollable app list when the reported app
count is unchanged AND the current menu already holds that many items.
If some getStandaloneAppInfo() calls failed transiently (e.g. an I2C
read glitch), the menu is incomplete; rebuilding on a later tick lets
it self-heal instead of staying permanently truncated.
Addresses Copilot review feedback on #3314.
* Refactor clock delays and improve JTAG runtest timing logic
* Refactor time calculations to use CH_FREQUENCY for consistency across modules
* Improve delay mechanism for reference oscillator startup in portapack_tcxo_enable
* comment
* increasing the time
* copilot
keeloqtx: Superrollo 67-bit transmit mode with rolling counter.
subghzd: GW60 receive decoder (reports as KeeLoq; manufacturer key read from KEELOQKEYS/MFCODES). The manufacturer key is not included; add a Superrollo entry to MFCODES to enable TX/RX.
GeoPos stored a coordinate's sign only in its degrees NumberField, which
is an int32_t and therefore has no negative zero. Any coordinate whose
integer degrees part is 0 but which is negative (i.e. strictly between
0.0 and -1.0) could not be represented at all:
- set_lat()/set_lon() passed the raw float to the degrees field, so
-0.2933 truncated to 0 and the sign was gone before it reached the
widget.
- lat()/lon() then decided the sign with `field_lon_degrees.value() < 0`,
which is false for 0, so the value came back positive.
The reporter's airport is at longitude -0.2933, which was impossible to
enter in the ADSB Tx app.
Give each coordinate an explicit hemisphere field (N/S and E/W) and make
the degrees field an unsigned magnitude:
- The hemisphere OptionsField is the single source of the sign, so
"negative with zero degrees" is now representable.
- set_lat()/set_lon() derive the hemisphere from the sign of the input
and feed the fields the magnitude.
- lat()/lon() read the hemisphere instead of inferring the sign from
the degrees value.
- The minutes on_wrap handlers no longer need to flip the carry
direction based on the degrees sign, since degrees is now a
magnitude; the carry is the same in both hemispheres.
- The degrees fields no longer loop, so carrying below 0 clamps at 0
instead of wrapping round to 90/180.
The hemisphere indicator occupies the column that the 4-wide signed
degrees field used for its minus sign, so the row layout, the degree
symbol and the decimal readout all stay where they were.
Fixes#3234
* Initial plan
* Fix ADSB altitude integer overflow and add on-ground indicator
- Fix display overflow: use to_string_dec_int (signed) instead of
to_string_dec_uint (unsigned) for altitude display - per ICAO Annex 10
Vol IV 3.1.2.6.5.4, altitude = 25N-1000 can be as low as -1000ft
- Remove incorrect altitude clamp (altitude < 0 => 0) in DF 0/4/20 decoder
- Add on_ground flag to AircraftRecentEntry; set from TC 5-8 (surface
position) messages, cleared on TC 9-22 (airborne position) messages
- Display 'GND' in altitude column when aircraft is on ground
- Clear altitude to 0 when on_ground is set to prevent stale data in map
color calculation
Closes#3274
* Revert on-ground indicator; keep only the overflow and clamp fixes
Remove on_ground field, TC 5-8 handling, and "GND" display per review
feedback. Only keep the two minimal bug fixes:
- Signed altitude display (to_string_dec_int vs to_string_dec_uint)
- Remove erroneous altitude < 0 clamp; update comment to show the math
* Update BEACONS.TXT
Added test beacon with 3 bch1 errors and 2 bch2 errors to test multiple bit error correction.
* Fist step to SGB format
* Added SGB to manual mode.
* SGB support
- Added SGB frame to beacons file
- Fixed hex display for SGB
- Fixed frame type option display
- Fixed self-test mode activation logic
- Fixed PRN for self-test mode
* First test
* Reorder includes for consistency and fix string dereference in VorCdiIndicator
* Add memory section and linker script entry for vor_rx application
* Testing VOR TX
* Moving VOR TX to SD
* Code refactoring to align with guidelines
* Add TODO comment to verify radial sign convention in vor_tx_config
* Remove unnecessary set_dirty() calls in VorRxView methods
* Update Course Deviation Indicator label and adjust UI element positions
* Update VorTxView to run prepared image from memory map
* Update build condition in nightly release workflow to include workflow_dispatch event
* Reverting action changes
* Adjust Course Deviation Indicator layout and refine painting logic
* Refactor VorRxView UI elements for improved layout and clarity
* Add calibration field and update radial calculation logic in VorRxView
* Enhance VOR processing: add renormalization to phase oscillator, improve signal handling, and update configuration parameters
* Implement radial smoothing and TO/FROM state handling in VorRxView; update VOR processing logic
* Setting comments inline
* Refactor VorCdiIndicator and VorRxView: change normalize_signed_degrees to use int32_t, update radial smoothing to use fixed point arithmetic to reduce flash usage
* Update external app address end to 0xAE0B0000
* Update set_vor_tx_config to include enabled parameter for consistency
* Refactor VorRx to omit decim_2 stage and update comments for clarity on VOR processing
* Add RSSI, Channel, and Audio fields to VorRxView to mimic existing apps
* Refactor VorRxView labels and status messages
* Update VorRxView calibration field range to allow full circle input
* Completing Ident transmission logic
* Fixing TX gain and moving log label
* Refactor VOR phase calculations and update radial offset handling for accurate bearing representation
* Add low-pass filters to strip 9960 Hz subcarrier from audio output
* Refactor GPIO mappings and definitions for improved clarity and functionality
- Updated SCU_ARRAY_SIZE definitions in pal_lld.h for PRALINE and non-PRALINE configurations.
- Modified pin mappings in gpio.hpp to reflect new hardware configurations, including additional control pins for RF and audio components.
- Removed obsolete GPIO definitions from hackrf_gpio.hpp and streamlined the code for better maintainability.
- Added new GPIO definitions for mix bypass, amplifier control, and other RF-related functionalities to enhance the system's capabilities.
* Refactor GPIO mappings and update SCU_ARRAY_SIZE for LPC43xx platform
- Updated SCU_ARRAY_SIZE to 80 for PRALINE configuration and 58 for others.
- Added new GPIO mappings for auxiliary power control, antenna bias, and R9 clock enable signals in gpio.hpp.
- Removed commented-out PPS output mapping in hackrf_gpio.hpp.
- Adjusted GPIO definitions for R9 clock signals to ensure proper functionality.
* Refactor RF path initialization and configuration for improved clarity and functionality
* Refactor RF path configuration and GPIO mappings for improved clarity and functionality
* Potential fix for pull request finding
* comment
* aux power polarrity
* Fix formatting of pin_aux_power_enable declaration
* The LNA gain field 'L' lives in LPF_VGA_2 (reg 6), not RXRF_2 (reg 2). RXRF_2 only holds LNAgain_SPI_EN. The configure_rx_gain() function wrote 'L' into lpf_vga_2 but marked RXRF_2 dirty => the LNA value only got flushed incidentally because the following VGA write marks LPF_VGA_2 dirty. Drop the stray RXRF_2 dirty flag and rely on the LPF_VGA_2 flag, which carries both L and VGA.
* The baseband build defined IS_H1_R9 as the compile-time constant 0, on the (now incorrect) assumption that detected_platform() isn't linked. The sd_over_usb image is the only baseband target that compiles the IS_H1_R9-gated upstream files (rf_path.c, si5351c.c, sgpio.c, platform_gpio.c, platform_scu.c), and it *does* link platform_detect.c and call detect_hardware_platform() at startup. Forcing IS_H1_R9=0 dead-stripped every 'if (IS_H1_R9)' branch, so a real HackRF One r9 was set up with the OG clock/GPIO/RF-path config in that image.
Define IS_H1_R9 as the runtime '(detected_platform()==BOARD_ID_HACKRF1_R9)', mirroring upstream platform-detect.cmake for HACKRF_ONE. All usages are '#ifdef IS_H1_R9' + 'if (IS_H1_R9)' (no arithmetic '#if'), so a function-call expression is safe, single-quoted -D with no internal spaces keeps it intact through the shell-split DDEFS blob.
---------
Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
* Refactor GPIO configuration for PRALINE and non-PRALINE setups
- Updated PinMap structure to include gpio_mode for better flexibility.
- Added new GPIO mappings for SGPIO pins with appropriate configurations.
- Commented out unused GPIO definitions in hackrf_gpio.hpp to improve code clarity.
- Adjusted GPIO initialization for control pins to utilize the new PinMap structure.
- Ensured compatibility for both PRALINE and non-PRALINE configurations by using preprocessor directives.
* Refactor GPIO handling and remove LED abstraction
- Updated GPIO class to support logical polarity, enabling/disabling features based on their configured state.
- Replaced direct GPIO manipulation in power control functions with new GPIO methods for better readability and maintainability.
- Removed the LED class and its associated functionality, as it was deemed unnecessary for the current implementation.
- Adjusted GPIO initialization for various components, ensuring correct polarity settings for VAA and power enable pins.
- Cleaned up unused includes and commented-out code in hackrf_gpio.hpp.
* Refactor GPIO LED control methods to use setActive() and setInactive() for improved clarity
* Refactor GPIO control methods to use setActive() and setInactive() for improved clarity and consistency
* copilot
* Update GPIO control logic and pin definitions for clarity and consistency
* Refactor GPIO methods for improved naming consistency and clarity
* update submodule to latest GSG modifications
* build: fix delay function
* update submodule to include praline fix
* fix dep to rebuild/reinclude hackrf_usb_ram.bin
* Implement antenna bias control for Praline and update GPIO configurations
* Add GPIO power management functions and update board initialization for Praline
* Refactor power management functions for Praline and update GPIO configurations
* Update GPIO configurations for Praline and enable power control pins. AA_EN enabled
* Refactor GPIO configuration for Praline: update array size definitions and clean up comments
* Add P1 and P2 control functions for PRALINE
* Introduced P1_Function and P2_Function enums in ClockManager to manage multiplexer control.
* mplemented set_p1_control and set_p2_control methods for configuring P1 and P2 control pins based on specified functions.
* Updated clock_manager.hpp and clock_manager.cpp to include new functionality.
* Modified MAX2837 and MAX2839 initialization to conditionally configure GPIO based on PRALINE.
* Adjusted RFFC507x and RFFC507x_SPI initialization to include GPIO setup for PRALINE.
- Refactored RF path initialization to remove unnecessary GPIO setup.
- Updated board configuration for PRALINE to reflect new GPIO settings and pin configurations.
- Cleaned up FPGA bridge code by removing unused pin configuration functions.
- Adjusted SCU array size in pal_lld.h for PRALINE.
- Enhanced hackrf_gpio.hpp to define multiplexer control pins for PRALINE.
- Modified LED setup to accommodate active-low configuration for PRALINE.
* Refactor GPIO and power control functions
- Removed unused power control function declarations from board.h.
- Enhanced gpio.hpp with new pin setup functions and GPIO control structures for PRALINE.
- Consolidated multiplexer control pin definitions into gpio_control namespace.
- Moved power control function implementations to gpio.cpp, including detailed VAA power management logic.
- Updated power control functions to handle both PRALINE and HackRF R9 configurations.
- Cleaned up hackrf_gpio.hpp by removing redundant multiplexer control definitions.
* Refactor GPIO control for PRALINE: update MAX2831 and RFFC507x configurations, add new GPIO mappings
* Refactor GPIO configurations for PRALINE: update anti-aliasing filter pin mapping, enhance LED setup logic, and add placeholder GPIO entries.
* Refactor GPIO configurations for PRALINE: update LED mappings and remove unused anti-aliasing filter GPIO entry.
* EPIRB RX: add receiver-overload indicator on channel bar
Tint the channel-power bar red when the front-end overloads (ADC near
full scale). EPIRB demodulation relies on the constant-envelope carrier
and the +/-1.1 rad biphase phase jumps; ADC clipping distorts both, so a
visible cue to reduce RF-amp/LNA/VGA gain is useful.
Implemented in the shared ui::Channel widget via an opt-in
set_overload_threshold(): when the last ChannelStatistics max_db reaches
the threshold the bar is drawn red instead of blue. Default threshold is
above the 0 dBFS ceiling, so all existing users are unaffected. The
EPIRB view enables it at -3 dBFS.
Done in the widget (main firmware) rather than the EPIRB app because the
epirb_rx external app is already at the 32 KB flash limit; the app only
pays for a single setter call.
* EPIRB RX: widen AFC capture range to +/-5 kHz
The AFC estimate was only applied after carrier lock, so carrier
acquisition ran on raw phase deltas and could only tolerate offsets of
a few hundred Hz before the 0.6/0.7/1.6 rad detection thresholds (on
the 12-sample accumulator) broke down.
Track the carrier offset continuously in the IDLE state with a
first-order loop (AFC_TRACK_ALPHA), so the de-biased accumulator
self-centers for any offset within the discriminator Nyquist (~24 kHz)
*before* the thresholds run. ALPHA = 0.005 pulls a +/-5 kHz offset
under the 0.6 rad lock threshold in ~11 ms, well inside the 160 ms
preamble / 80 ms stability window. The IDLE rise-detect threshold is
also made symmetric (fabsf) now that the bias is removed.
Also add the missing <cstdint> include to test_convert.cpp so the
application_test suite compiles under the current toolchain.
Verified: baseband_epirb_rx.elf builds (flash 53%, RAM 12%) and
baseband_test passes.
* indicate batt changed event
* added sleep config, and use it.
* reinit if new batt detected.
* more detect
* repl batt setting
* disabled some things
* copilot fixes
* fix clock init and add mayhem tx capacity
* aligned external clock and RX config
* fix(clock): cap TX interpolation to x16 to prevent doubled waveform speed
The TX gateware only implements interpolation factors x1..x16 (tx_intrp
0..4), but the rate search could select n==5 (x32) for very low TX
sample rates. That left the AFE/CLK0/CLK1 running at the x32 rate while
the FPGA only interpolated by x16, clocking the TX datapath at twice the
gateware output rate. Cap afe_rate and _resampling_n to the x16 limit in
TX so the clocks stay aligned with the interpolation setting.
* fix(praline): source PLL1 from 40MHz GP_CLKIN instead of 12MHz XTAL
For the intermediate 90-110MHz PLL1 stepping stage, source PLL1 from
GP_CLKIN (Si5351 CLK2/MCU_CLK at 40MHz) giving N=2, M=10, Fclk=100MHz,
rather than the on-chip 12MHz XTAL bootstrap path. This matches the
non-PRALINE path. Remove the dead commented-out XTAL enable/PLL code.
* docs(fpga_bridge): correct register 0x03 description for PRALINE gateware
Register 0x03 is RX_DIGITAL_GAIN in RX and TX_NCO_CTRL in TX, not
RX_PSTEP.
* Fix fpga_tx_set_nco_enable to use FPGA_REG3_TX_NCO_CTRL (0x03)
Mo
qwer123
Matej Sochan
Brumi-2021
Pezsma
未来方舟
rollorentner
Bernd Herzog
Oleg Belousov
MsfPablo
Copilot
qwer123
Frederic BORRY
Totoo
Luca
Sandbox
gullradriel
Synray
Arne Luehrs