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Gpio modify (#3229)

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* Refactor GPIO configuration for PRALINE and non-PRALINE setups

- Updated PinMap structure to include gpio_mode for better flexibility.
- Added new GPIO mappings for SGPIO pins with appropriate configurations.
- Commented out unused GPIO definitions in hackrf_gpio.hpp to improve code clarity.
- Adjusted GPIO initialization for control pins to utilize the new PinMap structure.
- Ensured compatibility for both PRALINE and non-PRALINE configurations by using preprocessor directives.

* Refactor GPIO handling and remove LED abstraction

- Updated GPIO class to support logical polarity, enabling/disabling features based on their configured state.
- Replaced direct GPIO manipulation in power control functions with new GPIO methods for better readability and maintainability.
- Removed the LED class and its associated functionality, as it was deemed unnecessary for the current implementation.
- Adjusted GPIO initialization for various components, ensuring correct polarity settings for VAA and power enable pins.
- Cleaned up unused includes and commented-out code in hackrf_gpio.hpp.

* Refactor GPIO LED control methods to use setActive() and setInactive() for improved clarity

* Refactor GPIO control methods to use setActive() and setInactive() for improved clarity and consistency

* copilot

* Update GPIO control logic and pin definitions for clarity and consistency

* Refactor GPIO methods for improved naming consistency and clarity
This commit is contained in:
Pezsma
2026-06-19 07:48:55 +02:00
committed by GitHub
parent 960e5b8329
commit cafe62564e
16 changed files with 634 additions and 569 deletions
Download Patch File Download Diff File Expand all files Collapse all files
firmware/application/apps/ui_debug.cpp
+2 -2
View File
@@ -3176,9 +3176,9 @@ void RFFC5072StatusView::refresh_status() {
// Blink LED
/*for (int i = 0; i < 3; i++) {
hackrf::one::led_rx.on();
hackrf::one::led_rx.setActive();
chThdSleepMilliseconds(100);
hackrf::one::led_rx.off();
hackrf::one::led_rx.setInactive();
chThdSleepMilliseconds(100);
}*/
} else {
firmware/application/clock_manager.cpp
+35 -33
View File
@@ -25,6 +25,8 @@
#include "portapack_io.hpp"
#include "portapack.hpp"
#include "lpc43xx.inc"
#include "hackrf_hal.hpp"
using namespace hackrf::one;
@@ -1211,47 +1213,47 @@ void ClockManager::enable_clock_output(bool enable) {
#ifdef PRALINE
void ClockManager::set_p1_control(P1_Function func) {
// Truth table based on P1_Control.csv (L=clear, H=set)
// Truth table based on P1_Control.csv (L=setInactive, H=setActive)
switch (func) {
case P1_Function::TriggerIn:
gpio_control::p1_ctrl2.clear();
gpio_control::p1_ctrl1.clear();
gpio_control::p1_ctrl0.clear();
gpio_control::p1_ctrl2.setInactive();
gpio_control::p1_ctrl1.setInactive();
gpio_control::p1_ctrl0.setInactive();
break;
case P1_Function::AuxClk1:
gpio_control::p1_ctrl2.clear();
gpio_control::p1_ctrl1.clear();
gpio_control::p1_ctrl0.set();
gpio_control::p1_ctrl2.setInactive();
gpio_control::p1_ctrl1.setInactive();
gpio_control::p1_ctrl0.setActive();
break;
case P1_Function::ClkIn:
gpio_control::p1_ctrl2.clear();
gpio_control::p1_ctrl1.set();
gpio_control::p1_ctrl0.clear();
gpio_control::p1_ctrl2.setInactive();
gpio_control::p1_ctrl1.setActive();
gpio_control::p1_ctrl0.setInactive();
break;
case P1_Function::TriggerOut:
gpio_control::p1_ctrl2.clear();
gpio_control::p1_ctrl1.set();
gpio_control::p1_ctrl0.set();
gpio_control::p1_ctrl2.setInactive();
gpio_control::p1_ctrl1.setActive();
gpio_control::p1_ctrl0.setActive();
break;
case P1_Function::P22_ClkIn:
gpio_control::p1_ctrl2.set();
gpio_control::p1_ctrl1.clear();
gpio_control::p1_ctrl0.clear();
gpio_control::p1_ctrl2.setActive();
gpio_control::p1_ctrl1.setInactive();
gpio_control::p1_ctrl0.setInactive();
break;
case P1_Function::P2_5:
gpio_control::p1_ctrl2.set();
gpio_control::p1_ctrl1.clear();
gpio_control::p1_ctrl0.set();
gpio_control::p1_ctrl2.setActive();
gpio_control::p1_ctrl1.setInactive();
gpio_control::p1_ctrl0.setActive();
break;
case P1_Function::NotConnected:
gpio_control::p1_ctrl2.set();
gpio_control::p1_ctrl1.set();
gpio_control::p1_ctrl0.clear();
gpio_control::p1_ctrl2.setActive();
gpio_control::p1_ctrl1.setActive();
gpio_control::p1_ctrl0.setInactive();
break;
case P1_Function::AuxClk2:
gpio_control::p1_ctrl2.set();
gpio_control::p1_ctrl1.set();
gpio_control::p1_ctrl0.set();
gpio_control::p1_ctrl2.setActive();
gpio_control::p1_ctrl1.setActive();
gpio_control::p1_ctrl0.setActive();
break;
}
}
@@ -1259,20 +1261,20 @@ void ClockManager::set_p1_control(P1_Function func) {
void ClockManager::set_p2_control(P2_Function func) {
// Ensure all P2 control pins are configured as outputs
// Truth table based on P2_Control.csv (L=clear, H=set)
// Truth table based on P2_Control.csv (L=setInactive, H=setActive)
switch (func) {
case P2_Function::Clk3:
// CTRL0 is 'X' (don't care) according to CSV, we default it to Low (clear)
gpio_control::p2_ctrl1.clear();
gpio_control::p2_ctrl0.clear();
// CTRL0 is 'X' (don't care) according to CSV, we default it to Low (setInactive)
gpio_control::p2_ctrl1.setInactive();
gpio_control::p2_ctrl0.setInactive();
break;
case P2_Function::TriggerIn:
gpio_control::p2_ctrl1.set();
gpio_control::p2_ctrl0.clear();
gpio_control::p2_ctrl1.setActive();
gpio_control::p2_ctrl0.setInactive();
break;
case P2_Function::TriggerOut:
gpio_control::p2_ctrl1.set();
gpio_control::p2_ctrl0.set();
gpio_control::p2_ctrl1.setActive();
gpio_control::p2_ctrl0.setActive();
break;
}
}
firmware/application/config_mode.cpp
+15 -10
View File
@@ -24,6 +24,11 @@
#include "hackrf_gpio.hpp"
#include "portapack_hal.hpp"
#include "board.h"
#include "gpio.hpp"
using namespace gpio_control;
void config_mode_blink_until_dfu();
void config_mode_set() {
@@ -103,16 +108,16 @@ void config_mode_run() {
auto tx_value = ((tx_blink_pattern >> ((counter >> 0) & 31)) & 0x1) == 0x1;
if (tx_value) {
hackrf::one::led_tx.on();
led_tx.setActive();
} else {
hackrf::one::led_tx.off();
led_tx.setInactive();
}
auto rx_value = ((rx_blink_pattern >> ((counter >> 0) & 31)) & 0x1) == 0x1;
if (rx_value) {
hackrf::one::led_rx.on();
led_rx.setActive();
} else {
hackrf::one::led_rx.off();
led_rx.setInactive();
}
chThdSleepMilliseconds(100);
@@ -122,14 +127,14 @@ void config_mode_run() {
void config_mode_blink_until_dfu() {
while (true) {
hackrf::one::led_tx.on();
hackrf::one::led_rx.on();
hackrf::one::led_usb.on();
led_tx.setActive();
led_rx.setActive();
led_usb.setActive();
chThdSleepMilliseconds(10);
hackrf::one::led_tx.off();
hackrf::one::led_rx.off();
hackrf::one::led_usb.off();
led_tx.setInactive();
led_rx.setInactive();
led_usb.setInactive();
chThdSleepMilliseconds(115);
auto dfu_btn = portapack::gpio_dfu.read();
firmware/application/debug.cpp
+5 -2
View File
@@ -33,6 +33,9 @@
#include "irq_controls.hpp"
#include "file_path.hpp"
#include "gpio.hpp"
using namespace gpio_control;
using namespace ui;
#define DEBUG_LOG_FILE "debug_log.txt"
@@ -134,9 +137,9 @@ void draw_line(int32_t y_offset, const char* label, regarm_t value) {
}
void runtime_error(uint8_t source) {
LED led = (source == CORTEX_M0) ? hackrf::one::led_rx : hackrf::one::led_tx;
const auto& led = (source == CORTEX_M0) ? led_rx : led_tx;
led.off();
led.setInactive();
// wait for DFU button release if pressed, so we don't immediately jump into stack dump
while (swizzled_switches() & (1 << (int)Switch::Dfu));
firmware/application/event_m0.cpp
+12 -14
View File
@@ -37,8 +37,8 @@
#include "ch.h"
#include "hackrf_gpio.hpp"
using namespace hackrf::one;
#include "gpio.hpp"
using namespace gpio_control;
#include "irq_rtc.hpp"
@@ -56,8 +56,6 @@ using namespace hackrf::one;
#include "ui_navigation.hpp"
#include "gpio.hpp"
static int delayed_error = 0;
extern "C" {
@@ -229,8 +227,8 @@ void EventDispatcher::charge_deep_sleep(const bool sleep) {
LPC_ADC0->CR &= ~(1 << 21);
LPC_ADC1->CR &= ~(1 << 21);
led_rx.off();
led_usb.off();
led_rx.setInactive();
led_usb.setInactive();
rtc_wakeup_init();
NVIC_EnableIRQ(I2C0_OR_I2C1_IRQn);
@@ -247,21 +245,21 @@ void EventDispatcher::charge_deep_sleep(const bool sleep) {
if (is_full) {
// Case 1: Battery full (All LEDs off)
led_rx.off();
led_tx.off();
led_rx.setInactive();
led_tx.setInactive();
} else if ((voltage < 4150 && current < 10) || valid_mask == 0) {
// Case 2: Not full but low current draw (<10mA) -> Charging error
led_tx.on(); // LED indicates error/idle
led_rx.off();
led_tx.setActive(); // LED indicates error/idle
led_rx.setInactive();
} else {
// Case 3: Actively charging
led_rx.on(); // LED indicates charging
led_tx.off();
led_rx.setActive(); // LED indicates charging
led_tx.setInactive();
}
} else {
// Case 4: Battery IC not detected -> Error or H2 or older, so don't show that as an error.
led_tx.on();
led_rx.on();
led_tx.setActive();
led_rx.setActive();
}
// Shut down I2C and power down the APB bus for sleep
firmware/application/hw/max2831.cpp
+2 -2
View File
@@ -347,9 +347,9 @@ void MAX2831::set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) {
* external Anti-Aliasing (AA) filter on pin P1_14 to prevent aliasing.
*/
if (actual_bw <= 1750000) {
gpio_control::aa_en.set(); // Enable external narrow AA filter
gpio_control::aa_en.setActive(); // Enable external narrow AA filter
} else {
gpio_control::aa_en.clear(); // Disable external AA filter for wideband operations
gpio_control::aa_en.setInactive(); // Disable external AA filter for wideband operations
}
_desired_lpf_bw = actual_bw;
firmware/application/hw/rffc507x.cpp
+1 -1
View File
@@ -176,7 +176,7 @@ struct SynthConfig {
void RFFC507x::init() {
#ifdef PRALINE
gpio_control::rf5072_mix_en.set(); // RF5072_MIX_EN
gpio_control::rf5072_mix_en.setActive(); // RF5072_MIX_EN
#endif
gpio_rffc5072_resetx.set();
firmware/application/main.cpp
-1
View File
@@ -132,7 +132,6 @@ Continuous (Fox-oring)
#include "spi_image.hpp"
#include "debug.hpp"
#include "led.hpp"
#include "gcc.hpp"
firmware/application/radio.cpp
+7 -4
View File
@@ -53,6 +53,9 @@ using namespace hackrf::one;
#include "baseband_api.hpp"
#include "hal.h" // For LPC_SGPIO
#include "gpio.hpp"
using namespace gpio_control;
#include <array>
/* Direct access to the radio. Setting values incorrectly can damage
@@ -280,9 +283,9 @@ void set_direction(const rf::Direction new_direction) {
baseband_codec.set_mode((direction == rf::Direction::Transmit) ? max5864::Mode::Transmit : max5864::Mode::Receive);
if (direction == rf::Direction::Receive)
led_rx.on();
led_rx.setActive();
else
led_tx.on();
led_tx.setActive();
}
bool set_tuning_frequency(const rf::Frequency frequency) {
@@ -442,8 +445,8 @@ void disable() {
first_if.disable();
set_rf_amp(false);
led_rx.off();
led_tx.off();
led_rx.setInactive();
led_tx.setInactive();
}
#ifdef PRALINE
firmware/application/transmitter_model.cpp
+3 -1
View File
@@ -26,7 +26,9 @@
#include "audio.hpp"
#include "baseband_api.hpp"
#include "event_m0.hpp"
#include "hackrf_gpio.hpp"
#include "gpio.hpp"
using namespace gpio_control;
#include "portapack.hpp"
#include "portapack_persistent_memory.hpp"
#include "radio.hpp"
firmware/chibios-portapack/boards/PORTAPACK_APPLICATION/board.cpp
+304 -300
View File
@@ -21,6 +21,7 @@
#include <array>
#include "gpio.hpp"
using namespace gpio_control;
// Declare wrapper function. board.cpp to avoid conflicting gpio_t definitions.
bool hackrf_r9;
@@ -56,55 +57,55 @@ const PALConfig pal_default_config = {
// GPIO0
.data
#ifdef PRALINE
= (0 << 7) // P2_7: Input GND
| (0 << 8) // P1_1: Input GND
| (1 << 9) // P1_2: Input VCC
| boot_bit(gpio_control::p1_ctrl0, 0) // P2_10: P1_CTRL0, start low
| (0 << 15) // P1_20: CLKIN_CTRL - start low
= (0 << 7) // P2_7: Input GND
| (0 << 8) // P1_1: Input GND
| (1 << 9) // P1_2: Input VCC
| boot_bit(p1_ctrl0, 0) // P2_10: P1_CTRL0, start low
| boot_bit(clkin_ctrl, 0) // P1_20: CLKIN_CTRL - start low
#else
= (1 << 14) // P2_10: AMP_BYPASS
| (1 << 15) // P1_20: CS_XCVR
#endif
| (1 << 11) // P1_4: SSP1_MOSI
| (0 << 13) // P1_18: SGPIO12, HOST_Q_INVERT
| (0 << 12) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
| (1 << 10) // P1_3: SSP1_MISO
| (0 << 9) // P1_2: Varies by revision, float until detection
| (0 << 8) // P1_1: Varies by revision, float until detection
| (0 << 7) // P2_7: Varies by revision, float until detection
| (0 << 6) // P3_6: SPIFI_MISO
| (1 << 5) // P6_6: SGPIO5, HOST_DATA5, Praline: FPGA HOST_DATA5
| (1 << 4) // P1_0: SGPIO7, HOST_DATA7, Praline: FPGA HOST_DATA7
| (1 << 3) // P1_16: SGPIO3, HOST_DATA3, Praline: FPGA HOST_DATA3
| (1 << 2) // P1_15: SGPIO2, HOST_DATA2, Praline: FPGA HOST_DATA2
| (1 << 1) // P0_1: SGPIO1, HOST_DATA1, Praline: FPGA HOST_DATA1
| (1 << 0) // P0_0: SGPIO0, HOST_DATA0, Praline: FPGA HOST_DATA0
| (1 << 11) // P1_4: SSP1_MOSI
| boot_bit(sgpio_12, 0) // P1_18: SGPIO12, HOST_Q_INVERT
| boot_bit(sgpio_11, 0) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
| (1 << 10) // P1_3: SSP1_MISO
| (0 << 9) // P1_2: Varies by revision, float until detection
| (0 << 8) // P1_1: Varies by revision, float until detection
| (0 << 7) // P2_7: Varies by revision, float until detection
| (0 << 6) // P3_6: SPIFI_MISO
| boot_bit(sgpio_5, 1) // P6_6: SGPIO5, HOST_DATA5, Praline: FPGA HOST_DATA5
| boot_bit(sgpio_7, 1) // P1_0: SGPIO7, HOST_DATA7, Praline: FPGA HOST_DATA7
| boot_bit(sgpio_3, 1) // P1_16: SGPIO3, HOST_DATA3, Praline: FPGA HOST_DATA3
| boot_bit(sgpio_2, 1) // P1_15: SGPIO2, HOST_DATA2, Praline: FPGA HOST_DATA2
| boot_bit(sgpio_1, 1) // P0_1: SGPIO1, HOST_DATA1, Praline: FPGA HOST_DATA1
| boot_bit(sgpio_0, 1) // P0_0: SGPIO0, HOST_DATA0, Praline: FPGA HOST_DATA0
,
.dir
#ifdef PRALINE
= (0 << 7) // P2_7: Input
| (0 << 8) // P1_1: Input
| (0 << 9) // P1_2: Input
| boot_bit(gpio_control::p1_ctrl0, 1) // P2_10: P1_CTRL0
| (1 << 15) // P1_20: CLKIN_CTRL
= (0 << 7) // P2_7: Input
| (0 << 8) // P1_1: Input
| (0 << 9) // P1_2: Input
| boot_bit(p1_ctrl0, 1) // P2_10: P1_CTRL0
| boot_bit(clkin_ctrl, 1) // P1_20: CLKIN_CTRL
#else
= (1 << 14) // P2_10: AMP_BYPASS
| (1 << 15) // P1_20: CS_XCVR
#endif
| (0 << 11) // P1_4: SSP1_MOSI
| (1 << 13) // P1_18: SGPIO12, HOST_Q_INVERT
| (0 << 12) // P1_17: SGPIO11, HOST_DIRECTION
| (0 << 10) // P1_3: SSP1_MISO
| (0 << 9) // P1_2: Varies by revision, float until detection
| (0 << 8) // P1_1: Varies by revision, float until detection
| (0 << 7) // P2_7: Varies by revision, float until detection
| (0 << 6) // P3_6: SPIFI_MISO
| (0 << 5) // P6_6: SGPIO5, HOST_DATA5
| (0 << 4) // P1_0: SGPIO7, HOST_DATA7
| (0 << 3) // P1_16: SGPIO3, HOST_DATA3
| (0 << 2) // P1_15: SGPIO2, HOST_DATA2
| (0 << 1) // P0_1: SGPIO1, HOST_DATA1
| (0 << 0) // P0_0: SGPIO0, HOST_DATA0
| (0 << 11) // P1_4: SSP1_MOSI
| boot_bit(sgpio_12, 1) // P1_18: SGPIO12, HOST_Q_INVERT
| boot_bit(sgpio_11, 0) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
| (0 << 10) // P1_3: SSP1_MISO
| (0 << 9) // P1_2: Varies by revision, float until detection
| (0 << 8) // P1_1: Varies by revision, float until detection
| (0 << 7) // P2_7: Varies by revision, float until detection
| (0 << 6) // P3_6: SPIFI_MISO
| boot_bit(sgpio_5, 1) // P6_6: SGPIO5, HOST_DATA5
| boot_bit(sgpio_7, 1) // P1_0: SGPIO7, HOST_DATA7
| boot_bit(sgpio_3, 0) // P1_16: SGPIO3, HOST_DATA3
| boot_bit(sgpio_2, 0) // P1_15: SGPIO2, HOST_DATA2
| boot_bit(sgpio_1, 0) // P0_1: SGPIO1, HOST_DATA1
| boot_bit(sgpio_0, 0) // P0_0: SGPIO0, HOST_DATA0
},
{
// GPIO1
@@ -112,15 +113,15 @@ const PALConfig pal_default_config = {
| (1 << 14) // P3_4: SPIFI_SIO3
| (1 << 13) // P2_13: PortaPack DIR
#ifdef PRALINE
| (1 << 12) // P2_12: BIAS_EN
| (0 << 11) // P2_11: BIAS_OC
| boot_bit(gpio_control::aa_en, 0) // P1_14: AA_EN
| (0 << 0) // P1_7: Output GND
| (1 << 12) // P2_12: BIAS_EN
| (0 << 11) // P2_11: BIAS_OC
| boot_bit(aa_en, 0) // P1_14: AA_EN
| (0 << 0) // P1_7: Output GND
#else
| (1 << 12) // P2_12: !RX_AMP_PWR
| (0 << 11) // P2_11: RX_AMP
| (1 << 7) // P1_14: SGPIO10, HOST_DISABLE
| (0 << 0) // P1_7: !MIX_BYPASS
| (1 << 12) // P2_12: !RX_AMP_PWR
| (0 << 11) // P2_11: RX_AMP
| boot_bit(sgpio_10, 1) // P1_14: SGPIO10, HOST_DISABLE
| (0 << 0) // P1_7: !MIX_BYPASS
#endif
| (0 << 10) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
| (1 << 9) // P1_6: SD_CMD
@@ -136,15 +137,15 @@ const PALConfig pal_default_config = {
| (0 << 14) // P3_4: SPIFI_SIO3
| (1 << 13) // P2_13: PortaPack DIR
#ifdef PRALINE
| (1 << 12) // P2_12: !BIAS_EN
| (0 << 11) // P2_11: BIAS_OC
| boot_bit(gpio_control::aa_en, 1) // P1_14: AA_EN
| (1 << 0) // P1_7: Output
| (1 << 12) // P2_12: !BIAS_EN
| (0 << 11) // P2_11: BIAS_OC
| boot_bit(aa_en, 1) // P1_14: AA_EN
| (1 << 0) // P1_7: Output
#else
| (1 << 12) // P2_12: !RX_AMP_PWR
| (1 << 11) // P2_11: RX_AMP
| (0 << 7) // P1_14: SGPIO10, HOST_DISABLE
| (1 << 0) // P1_7: !MIX_BYPASS
| (1 << 12) // P2_12: !RX_AMP_PWR
| (1 << 11) // P2_11: RX_AMP
| boot_bit(sgpio_10, 0) // P1_14: SGPIO10, HOST_DISABLE
| (1 << 0) // P1_7: !MIX_BYPASS
#endif
| (1 << 10) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
| (0 << 9) // P1_6: SD_CMD
@@ -161,31 +162,31 @@ const PALConfig pal_default_config = {
.data = (0 << 15) // P5_6: TX_AMP, unused on PRALINE
| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
#ifdef PRALINE
| (1 << 13) // P5_4: RFFC5072 ENX
| (0 << 12) // P5_3: unused on PRALINE
| (0 << 11) // P5_2: FPGA_CRESET
| (1 << 10) // P5_1: FPGA_SPI_CS
| (0 << 4) // P4_4: unused on PRALINE
| (0 << 0) // P4_0: unused on PRALINE
| (0 << 9) // P5_0: unused on PRALINE
| (0 << 3) // P4_3: VBUSCTRL input GND
| (1 << 6) // P4_6: Input VCC (10K PU)
| (1 << 8) // P6_12: LED3 (TX)
| (1 << 2) // P4_2: LED2 (RX)
| (1 << 1) // P4_1: LED1 (USB)
| (1 << 13) // P5_4: RFFC5072 ENX
| (0 << 12) // P5_3: unused on PRALINE
| (0 << 11) // P5_2: FPGA_CRESET
| (1 << 10) // P5_1: FPGA_SPI_CS
| (0 << 4) // P4_4: unused on PRALINE
| (0 << 0) // P4_0: unused on PRALINE
| (0 << 9) // P5_0: unused on PRALINE
| (0 << 3) // P4_3: VBUSCTRL input GND
| (1 << 6) // P4_6: Input VCC (10K PU)
| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
#else
| (1 << 13) // P5_4: MIXER_ENX, 10K PU
| (1 << 12) // P5_3: RX_MIX_BP
| (0 << 11) // P5_2: TX_MIX_BP
| (0 << 10) // P5_1: LP
| (0 << 4) // P4_4: Varies by revision
| (0 << 9) // P5_0: Varies by revision
| (1 << 0) // P4_0: HP
| (1 << 3) // P4_3: SGPIO9, HOST_CAPTURE
| (0 << 6) // P4_6: XCVR_EN, 10K PD
| (0 << 8) // P6_12: LED3 (TX)
| (0 << 2) // P4_2: LED2 (RX)
| (0 << 1) // P4_1: LED1 (USB)
| (1 << 13) // P5_4: MIXER_ENX, 10K PU
| (1 << 12) // P5_3: RX_MIX_BP
| (0 << 11) // P5_2: TX_MIX_BP
| (0 << 10) // P5_1: LP
| (0 << 4) // P4_4: Varies by revision
| (0 << 9) // P5_0: Varies by revision
| (1 << 0) // P4_0: HP
| boot_bit(sgpio_9, 1) // P4_3: SGPIO9, HOST_CAPTURE
| (0 << 6) // P4_6: XCVR_EN, 10K PD
| boot_bit(led_tx, 0) // P6_12: LED3 (TX)
| boot_bit(led_rx, 0) // P4_2: LED2 (RX)
| boot_bit(led_usb, 0) // P4_1: LED1 (USB)
#endif
| (1 << 7) // P5_7: CS_AD
@@ -203,22 +204,22 @@ const PALConfig pal_default_config = {
| (0 << 3) // P4_3: VBUSCTRL input
| (0 << 6) // P4_6: Input
#else
| (1 << 13) // P5_4: MIXER_ENX, 10K PU
| (1 << 12) // P5_3: RX_MIX_BP
| (1 << 11) // P5_2: TX_MIX_BP
| (1 << 10) // P5_1: LP
| (0 << 4) // P4_4: Varies by revision
| (0 << 9) // P5_0: Varies by revision
| (1 << 0) // P4_0: HP
| (0 << 3) // P4_3: SGPIO9, HOST_CAPTURE
| (1 << 6) // P4_6: XCVR_EN, 10K PD
| (1 << 13) // P5_4: MIXER_ENX, 10K PU
| (1 << 12) // P5_3: RX_MIX_BP
| (1 << 11) // P5_2: TX_MIX_BP
| (1 << 10) // P5_1: LP
| (0 << 4) // P4_4: Varies by revision
| (0 << 9) // P5_0: Varies by revision
| (1 << 0) // P4_0: HP
| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
| (1 << 6) // P4_6: XCVR_EN, 10K PD
#endif
| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
| (1 << 8) // P6_12: LED3 (TX)
| (1 << 7) // P5_7: CS_AD
| (1 << 5) // P4_5: RXENABLE
| (1 << 2) // P4_2: LED2 (RX)
| (1 << 1) // P4_1: LED1 (USB)
| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
| (1 << 7) // P5_7: CS_AD
| (1 << 5) // P4_5: RXENABLE
| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
},
{
// GPIO3
@@ -231,16 +232,16 @@ const PALConfig pal_default_config = {
| (1 << 9) // P7_1: PortaPack GPIO3_9(IO)
| (1 << 8) // P7_0: PortaPack GPIO3_8(IO)
#ifdef PRALINE
| (0 << 4) // P6_5: TX_ENABLE
| (1 << 2) // P6_3: MIX_ENABLE_N
| (0 << 6) // P6_10: unused on PRALINE
| boot_bit(gpio_control::p1_ctrl2, 0) // P6_9: P1_CTRL2
| (0 << 4) // P6_5: TX_ENABLE
| (1 << 2) // P6_3: MIX_ENABLE_N
| (0 << 6) // P6_10: unused on PRALINE
| boot_bit(p1_ctrl2, 0) // P6_9: P1_CTRL2
#else
| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
| (1 << 7) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| (1 << 2) // P6_3: SGPIO4, HOST_DATA4
| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
| boot_bit(vregmode, 1) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| (1 << 2) // P6_3: SGPIO4
| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
#endif
| (1 << 3) // P6_4: MIXER_SDATA
| (1 << 1) // P6_2: HackRF CPLD.TDI(I)
@@ -255,16 +256,16 @@ const PALConfig pal_default_config = {
| (1 << 9) // P7_1: PortaPack GPIO3_9(IO)
| (1 << 8) // P7_0: PortaPack GPIO3_8(IO)
#ifdef PRALINE
| (0 << 7) // P6_11: 3V3AUX_OC
| (1 << 4) // P6_5: TX_ENABLE
| (1 << 2) // P6_3: MIX_ENABLE_N
| (0 << 6) // P6_10: unused on PRALINE
| boot_bit(gpio_control::p1_ctrl2, 1) // P6_9: P1_CTRL2
| (0 << 7) // P6_11: 3V3AUX_OC
| (1 << 4) // P6_5: TX_ENABLE
| (1 << 2) // P6_3: MIX_ENABLE_N
| (0 << 6) // P6_10: unused on PRALINE
| boot_bit(p1_ctrl2, 1) // P6_9: P1_CTRL2
#else
| (1 << 7) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| (0 << 2) // P6_3: SGPIO4, HOST_DATA4
| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
| boot_bit(vregmode, 1) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| (0 << 2) // P6_3: SGPIO4
| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
#endif
| (0 << 4) // P6_5: HackRF CPLD.TMS(I)
| (0 << 3) // P6_4: MIXER_SDATA
@@ -274,63 +275,65 @@ const PALConfig pal_default_config = {
{
// GPIO4
.data =
boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
#ifdef PRALINE
(0 << 9) // PA_2: RF_AMP_EN
| (0 << 8) // PA_1: LPF_EN
| (0 << 7) // P8_7: 1V2_EN
| (1 << 6) // P8_6: LED4
| (0 << 5) // P8_5: VIN_IN_EN
| (0 << 4) // P8_4: VBUS_IN_EN
| (1 << 1) // P8_1: VAA_EN
| (0 << 10) // PA_3: Output GND
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(gpio_control::rf5072_mix_en, 0) // P9_0: RF5072 enable
| (0 << 13) // P9_1: Output GND
| (0 << 14) // P9_2: RFFC5072 SDATA
| (0 << 3) // P8_3: Output GND
#else
(1 << 11) // P9_6: SGPIO8, SGPIO_CLK, HackRF MAX2831 LD
| (0 << 9) // PA_2: RF_AMP_EN
| (0 << 8) // PA_1: LPF_EN
| boot_bit(en_1v2, 0) // P8_7: EN_1V2
| boot_bit(led_mcu, 1) // P8_6: LED4
| boot_bit(sgpio_10, 1) // P8_2: SGPIO10, HOST_DISABLE
| (0 << 5) // P8_5: VIN_IN_EN
| (0 << 4) // P8_4: VBUS_IN_EN
| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
| (0 << 10) // PA_3: Output GND
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(rf5072_mix_en, 0) // P9_0: RF5072 enable
| (0 << 13) // P9_1: Output GND
| (0 << 14) // P9_2: RFFC5072 SDATA
| (0 << 3) // P8_3: Output GND
| boot_bit(sgpio_9, 1) // P9_3: Capture Input
#endif
,
.dir =
boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
#ifdef PRALINE
(1 << 9) // PA_2: RF_AMP_EN
| (1 << 8) // PA_1: LPF_EN
| (1 << 7) // P8_7: 1V2_EN
| (1 << 6) // P8_6: LED4
| (1 << 5) // P8_5: VIN_IN_EN
| (1 << 4) // P8_4: VBUS_IN_EN
| (1 << 1) // P8_1: VAA_EN
| (1 << 10) // PA_3: Output
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(gpio_control::rf5072_mix_en, 1) // P9_0: RF5072 enable
| (1 << 13) // P9_1: Output
| (0 << 14) // P9_2: RFFC5072 SDATA (Bidirectional)
| (1 << 3) // P8_3: Output
#else
(1 << 11) // P9_6: SGPIO8, SGPIO_CLK, HackRF MAX2831 LD
| (1 << 9) // PA_2: RF_AMP_EN
| (1 << 8) // PA_1: LPF_EN
| boot_bit(en_1v2, 1) // P8_7: EN_1V2
| boot_bit(led_mcu, 1) // P8_6: LED4
| boot_bit(sgpio_10, 0) // P8_2: SGPIO10, HOST_DISABLE
| (1 << 5) // P8_5: VIN_IN_EN
| (1 << 4) // P8_4: VBUS_IN_EN
| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
| (1 << 10) // PA_3: Output
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(rf5072_mix_en, 1) // P9_0: RF5072 enable
| (1 << 13) // P9_1: Output
| (0 << 14) // P9_2: RFFC5072 SDATA (Bidirectional)
| (1 << 3) // P8_3: Output
| boot_bit(sgpio_9, 0) // P9_3: Capture Input
#endif
},
{
// GPIO5
.data =
#ifdef PRALINE
(0 << 18) // P9_5: RFF5072 SCLK
| boot_bit(gpio_control::trigger_out, 0) // P2_6: Trigger out
| (0 << 14) // P4_10: FPGA CDONE
| (1 << 15) // P6_7: 3V3 AUX_ENABLE
| boot_bit(gpio_control::p1_ctrl1, 0) // P6_8: P1_CTRL1
| (0 << 17) // P9_4: FPGA SGPIO
| (0 << 19) // PA_4: Output GND
| (0 << 20) // PB_0: Output GND
| (0 << 21) // PB_1: Output GND
| (0 << 22) // PB_2: Unused IN
| (0 << 23) // PB_3: Output GND
| (0 << 24) // PB_4: Unused IN
| (0 << 25) // PB_5: Output GND
| (0 << 5) // P2_5: PPS OUT/IN
| (0 << 12) // P4_8: Output GND
| (0 << 13) // P4_9: TPS62410 VREGMODE
(0 << 18) // P9_5: RFF5072 SCLK
| boot_bit(trigger_out, 0) // P2_6: Trigger out
| (0 << 14) // P4_10: FPGA CDONE
| (1 << 15) // P6_7: 3V3 AUX_ENABLE
| boot_bit(p1_ctrl1, 0) // P6_8: P1_CTRL1
| boot_bit(sgpio_4, 1) // P9_4: FPGA SGPIO4
| (0 << 19) // PA_4: Output GND
| (0 << 20) // PB_0: Output GND
| (0 << 21) // PB_1: Output GND
| (0 << 22) // PB_2: Unused IN
| (0 << 23) // PB_3: Output GND
| (0 << 24) // PB_4: Unused IN
| (0 << 25) // PB_5: Output GND
| (0 << 5) // P2_5: PPS OUT/IN
| (0 << 12) // P4_8: Output GND
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
#else
(1 << 18) // P9_5: HackRF CPLD.TDO(O)
| (0 << 6) // P2_6: MIXER_SCLK
@@ -341,35 +344,35 @@ const PALConfig pal_default_config = {
| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
| (0 << 12) // P4_8: Varies by revision
#endif
| (1 << 11) // P3_8: SPIFI_CS
| (1 << 10) // P3_7: SPIFI_MOSI
| (1 << 9) // P3_2: I2S0_RX_SDA
| (1 << 8) // P3_1: I2S0_RX_WS
| (0 << 7) // P2_8: BOOT2
| (1 << 4) // P2_4: PortaPack LCD_RDX
| (0 << 3) // P2_3: PortaPack LCD_TE
| (1 << 2) // P2_2: SGPIO6, HOST_DATA6
| (1 << 1) // P2_1: PortaPack ADDR
| (1 << 0) // P2_0: PortaPack IO_STBX
| (1 << 11) // P3_8: SPIFI_CS
| (1 << 10) // P3_7: SPIFI_MOSI
| (1 << 9) // P3_2: I2S0_RX_SDA
| (1 << 8) // P3_1: I2S0_RX_WS
| (0 << 7) // P2_8: BOOT2
| (1 << 4) // P2_4: PortaPack LCD_RDX
| (0 << 3) // P2_3: PortaPack LCD_TE
| boot_bit(sgpio_6, 1) // P2_2: SGPIO6, HOST_DATA6
| (1 << 1) // P2_1: PortaPack ADDR
| (1 << 0) // P2_0: PortaPack IO_STBX
,
.dir =
#ifdef PRALINE
(1 << 18) // P9_5: RFF5072 SCLK
| boot_bit(gpio_control::trigger_out, 1) // P2_6: Trigger out
| (0 << 14) // P4_10: FPGA CDONE
| (1 << 15) // P6_7: 3V3 AUX_ENABLE
| (1 << 16) // P6_8: P1_CTRL1
| (0 << 17) // P9_4: FPGA SGPIO
| (1 << 19) // PA_4: Output
| (1 << 20) // PB_0: Output GND
| (1 << 21) // PB_1: Output GND
| (0 << 22) // PB_2: Unused
| (1 << 23) // PB_3: Output
| (0 << 24) // PB_4: Unused
| (1 << 25) // PB_5: Output
| (0 << 5) // P2_5: PPS (Bidirectional)
| (1 << 12) // P4_8: Output
| (1 << 13) // P4_9: TPS62410 VREGMODE
(1 << 18) // P9_5: RFF5072 SCLK
| boot_bit(trigger_out, 1) // P2_6: Trigger out
| (0 << 14) // P4_10: FPGA CDONE
| (1 << 15) // P6_7: 3V3 AUX_ENABLE
| boot_bit(p1_ctrl1, 1) // P6_8: P1_CTRL1
| boot_bit(sgpio_4, 0) // P9_4: FPGA SGPIO
| (1 << 19) // PA_4: Output
| (1 << 20) // PB_0: Output GND
| (1 << 21) // PB_1: Output GND
| (0 << 22) // PB_2: Unused
| (1 << 23) // PB_3: Output
| (0 << 24) // PB_4: Unused
| (1 << 25) // PB_5: Output
| (0 << 5) // P2_5: PPS (Bidirectional)
| (1 << 12) // P4_8: Output
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
#else
(0 << 18) // P9_5: HackRF CPLD.TDO(O)
| (1 << 6) // P2_6: MIXER_SCLK
@@ -380,31 +383,31 @@ const PALConfig pal_default_config = {
| (0 << 13) // P4_9: SGPIO14, CPLD
| (0 << 12) // P4_8: Varies by revision
#endif
| (0 << 11) // P3_8: SPIFI_CS
| (0 << 10) // P3_7: SPIFI_MOSI
| (0 << 9) // P3_2: I2S0_RX_SDA
| (0 << 8) // P3_1: I2S0_RX_WS
| (0 << 7) // P2_8: BOOT2
| (0 << 4) // P2_4: PortaPack LCD_RDX
| (0 << 3) // P2_3: PortaPack LCD_TE
| (0 << 2) // P2_2: SGPIO6, HOST_DATA6
| (0 << 1) // P2_1: PortaPack ADDR
| (0 << 0) // P2_0: PortaPack IO_STBX
| (0 << 11) // P3_8: SPIFI_CS
| (0 << 10) // P3_7: SPIFI_MOSI
| (0 << 9) // P3_2: I2S0_RX_SDA
| (0 << 8) // P3_1: I2S0_RX_WS
| (0 << 7) // P2_8: BOOT2
| (0 << 4) // P2_4: PortaPack LCD_RDX
| (0 << 3) // P2_3: PortaPack LCD_TE
| boot_bit(sgpio_6, 0) // P2_2: SGPIO6, HOST_DATA6
| (0 << 1) // P2_1: PortaPack ADDR
| (0 << 0) // P2_0: PortaPack IO_STBX
},
{
// GPIO6
#ifdef PRALINE
.data = (1 << 28) // PD_14: MAX2831 chip select
| (0 << 29) // PD_15: MAX2831 RXHP control RXHP low = 100 Hz HPF
| (1 << 30) // PD_16: MAX5865 chip select
| (1 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(gpio_control::trigger_in, 0) // PD_12: TRIGGER IN
.data = (1 << 28) // PD_14: MAX2831 chip select
| (0 << 29) // PD_15: MAX2831 RXHP control RXHP low = 100 Hz HPF
| (1 << 30) // PD_16: MAX5865 chip select
| (1 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
,
.dir = (1 << 28) // PD_14: MAX2831 chip select
| (1 << 29) // PD_15: MAX2831 RXHP control
| (1 << 30) // PD_16: MAX5865 chip select
| (0 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(gpio_control::trigger_in, 0) // PD_12: TRIGGER IN
.dir = (1 << 28) // PD_14: MAX2831 chip select
| (1 << 29) // PD_15: MAX2831 RXHP control
| (1 << 30) // PD_16: MAX5865 chip select
| (0 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
#else
.data = 0,
.dir = 0
@@ -413,17 +416,17 @@ const PALConfig pal_default_config = {
{
// GPIO7
#ifdef PRALINE
.data = (0 << 0) // PE_0: Output
| (0 << 1) // PE_1: MAX2831 !SHDN
| (0 << 2) // PE_2: MAX2831 RXTX
| boot_bit(gpio_control::p2_ctrl0, 0) // PE_3: P2_ctrl0
| boot_bit(gpio_control::p2_ctrl1, 0) // PE_4: P2_ctrl1
.data = (0 << 0) // PE_0: Output
| (0 << 1) // PE_1: MAX2831 !SHDN
| (0 << 2) // PE_2: MAX2831 RXTX
| boot_bit(p2_ctrl0, 0) // PE_3: P2_ctrl0
| boot_bit(p2_ctrl1, 0) // PE_4: P2_ctrl1
,
.dir = (1 << 0) // PE_0: Output
| (1 << 1) // PE_1: MAX2831 !SHDN
| (1 << 2) // PE_2: MAX2831 RXTX
| boot_bit(gpio_control::p2_ctrl0, 1) // PE_3: P2_ctrl0
| boot_bit(gpio_control::p2_ctrl1, 1) // PE_4: P2_ctrl1
.dir = (1 << 0) // PE_0: Output
| (1 << 1) // PE_1: MAX2831 !SHDN
| (1 << 2) // PE_2: MAX2831 RXTX
| boot_bit(p2_ctrl0, 1) // PE_3: P2_ctrl0
| boot_bit(p2_ctrl1, 1) // PE_4: P2_ctrl1
#else
.data = 0,
.dir = 0
@@ -434,28 +437,28 @@ const PALConfig pal_default_config = {
// SClock LEDs
{4, 7, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // GP_CLKIN: SI5351C.CLK7(O)
{4, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED1: USB
{4, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED2: RX
{6, 12, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED3: TX
{4, 7, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // GP_CLKIN: SI5351C.CLK7(O)
{map_led_usb.scu_port, map_led_usb.scu_pin, scu_config_normal_drive_t{.mode = map_led_usb.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED1: USB
{map_led_rx.scu_port, map_led_rx.scu_pin, scu_config_normal_drive_t{.mode = map_led_rx.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED2: RX
{map_led_tx.scu_port, map_led_tx.scu_pin, scu_config_normal_drive_t{.mode = map_led_tx.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED3: TX
#ifdef PRALINE
{8, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED4: PRALINE Custom
{map_led_mcu.scu_port, map_led_mcu.scu_pin, scu_config_normal_drive_t{.mode = map_led_mcu.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // LED4: PRALINE Custom
#endif
// POWER MANAGEMENT (Regulators, Bias, Current Limits)
{6, 11, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // VREGMODE: TPS62410
{map_vregmode.scu_port, map_vregmode.scu_pin, scu_config_normal_drive_t{.mode = map_vregmode.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // VREGMODE: TPS62410
#ifdef PRALINE
{8, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_1: VAA_EN
{8, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_4: VBUS_IN_EN
{8, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_5: VIN_IN_EN
{8, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_7: 1V2_EN
{6, 7, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_7: 3.3V Aux Enable
{4, 9, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_9: TPS62410 mode
{gpio_control::map_p1_ctrl0.scu_port, gpio_control::map_p1_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = 0, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10: P1_CTRL0
{gpio_control::map_p1_ctrl2.scu_port, gpio_control::map_p1_ctrl2.scu_pin, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_9: P1_CTRL2 (Output VCC, PU ON,)
{gpio_control::map_p2_ctrl0.scu_port, gpio_control::map_p2_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_3: P2_CTRL0
{gpio_control::map_p2_ctrl1.scu_port, gpio_control::map_p2_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_4: P2_CTRL1
{map_VAA_en.scu_port, map_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_1: !VAA_EN
{8, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_4: VBUS_IN_EN
{8, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_5: VIN_IN_EN
{map_en_1v2.scu_port, map_en_1v2.scu_pin, scu_config_normal_drive_t{.mode = map_en_1v2.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_7: EN_1V2
{6, 7, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_7: 3.3V Aux Enable
{4, 9, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_9: TPS62410 mode
{map_p1_ctrl0.scu_port, map_p1_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl0.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10: P1_CTRL0
{map_p1_ctrl2.scu_port, map_p1_ctrl2.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl2.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_9: P1_CTRL2 (Output VCC, PU ON,)
{map_p2_ctrl0.scu_port, map_p2_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = map_p2_ctrl0.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_3: P2_CTRL0
{map_p2_ctrl1.scu_port, map_p2_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p2_ctrl1.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_4: P2_CTRL1
#endif
/* HackRF: I2C0 */
@@ -480,43 +483,41 @@ const PALConfig pal_default_config = {
}},
// FPGA & HIGH-SPEED DATA (SGPIO, Config, Triggers)
{0, 0, scu_config_normal_drive_t{.mode = 3, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO0: HOST_DATA0(IO)
{0, 1, scu_config_normal_drive_t{.mode = 3, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO1: HOST_DATA1(IO)
{1, 15, scu_config_normal_drive_t{.mode = 2, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO2: HOST_DATA2(IO)
{1, 16, scu_config_normal_drive_t{.mode = 2, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO3: HOST_DATA3(IO)
{6, 6, scu_config_normal_drive_t{.mode = 2, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO5: HOST_DATA5(IO)
{2, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO6: HOST_DATA6(IO)
{1, 0, scu_config_normal_drive_t{.mode = 6, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO7: HOST_DATA7(IO)
{1, 18, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO12: HOST_INVERT(I)
{map_sgpio_0.scu_port, map_sgpio_0.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_0.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO0: HOST_DATA0(IO)
{map_sgpio_1.scu_port, map_sgpio_1.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_1.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO1: HOST_DATA1(IO)
{map_sgpio_2.scu_port, map_sgpio_2.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_2.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO2: HOST_DATA2(IO)
{map_sgpio_3.scu_port, map_sgpio_3.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_3.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO3: HOST_DATA3(IO)
{map_sgpio_4.scu_port, map_sgpio_4.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_4.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO4 HOST_DATA4(IO)
{map_sgpio_5.scu_port, map_sgpio_5.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_5.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO5: HOST_DATA5(IO)
{map_sgpio_6.scu_port, map_sgpio_6.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_6.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO6: HOST_DATA6(IO)
{map_sgpio_7.scu_port, map_sgpio_7.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_7.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO7: HOST_DATA7(IO)
{map_sgpio_8.scu_port, map_sgpio_8.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_8.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO8: CLK
{map_sgpio_9.scu_port, map_sgpio_9.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_9.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO9: HOST_CAPTURE
{map_sgpio_10.scu_port, map_sgpio_10.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_10.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO10: DISABLE
{map_sgpio_11.scu_port, map_sgpio_11.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_11.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO11: HOST_DIRECTION(I)
{map_sgpio_12.scu_port, map_sgpio_12.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_12.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO12: HOST_INVERT(I)
#ifdef PRALINE
{8, 0, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO8: P8_0 func 4 (CLK)
{8, 2, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO10: P8_2 func 4 (DISABLE)
{9, 3, scu_config_normal_drive_t{.mode = 6, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO9: P9_3 func 6 (CAPTURE)
{9, 4, scu_config_normal_drive_t{.mode = 6, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO4: P9_4 func 6
{1, 17, scu_config_normal_drive_t{.mode = 6, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO11: P1_17 func 6 (DIRECTION)
{6, 4, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P6_4: SCT_CLK IN (Fast clock input, Mode 1)
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P4_10: FPGA Config Done (Input GND)
{gpio_control::map_trigger_in.scu_port, gpio_control::map_trigger_in.scu_pin, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_12: TRIGGER IN (Input GND, Mode 4)
{gpio_control::map_trigger_out.scu_port, gpio_control::map_trigger_out.scu_pin, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P2_6: TRIGGER
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P2_5: PPS OUT/IN (Mode 4 per Suppl. Data)
{6, 4, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P6_4: SCT_CLK IN (Fast clock input, Mode 1)
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P4_10: FPGA Config Done (Input GND)
{map_trigger_in.scu_port, map_trigger_in.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_in.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_12: TRIGGER IN (Input GND, Mode 4)
{map_trigger_out.scu_port, map_trigger_out.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_out.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P2_6: TRIGGER
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}},
{gpio_control::map_clkin_ctrl.scu_port, gpio_control::map_clkin_ctrl.scu_pin, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CLKIN_ctrl
#else
{9, 6, scu_config_normal_drive_t{.mode = 6, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // SGPIO8: SI5351C.CLK2(O)
{4, 3, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, // SGPIO9: HOST_CAPTURE(O)
{1, 14, scu_config_normal_drive_t{.mode = 6, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // SGPIO10: HOST_DISABLE(I)
{1, 17, scu_config_normal_drive_t{.mode = 6, .epd = 1, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // SGPIO11: HOST_DIRECTION(I)
{6, 3, scu_config_normal_drive_t{.mode = 2, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // SGPIO4: HOST_DATA4(IO)
{4, 9, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO14/BANK2F3M4: CPLD_P81
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO15/BANK2F3M6: CPLD_P78
{2, 6, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I)
{4, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // RXENABLE
{4, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // XCVR_EN: 10K PD
{1, 20, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I)
#endif
// RADIO & RF PATH (MAX2831, RFFC5072, Mixers, Switches, Amps)
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
{1, 20, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I)
{2, 11, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_11 RX_AMP
{2, 12, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_12 !RX_AMP_PWR
{4, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_0 HP
@@ -524,25 +525,24 @@ const PALConfig pal_default_config = {
{5, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_2 TX_MIX_BP
#ifdef PRALINE
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: RFFC ENX
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_5: RFFC RESETX
{9, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P9_5: RFFC5072 SCLK
{9, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P9_2: RFFC5072 DATA (Bidirectional)
{13, 11, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_11: RFFC Lock Detect
{13, 14, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_14: MAX2831 CS
{13, 15, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PD_15: MAX2831 RXHP
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
{14, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PE_1: MAX2831 !SHDN
{14, 2, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
{6, 3, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
{gpio_control::map_p1_ctrl1.scu_port, gpio_control::map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
{gpio_control::map_aa_en.scu_port, gpio_control::map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
{gpio_control::map_rf5072_mix_en.scu_port, gpio_control::map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = 0, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
{6, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: RFFC ENX
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_5: RFFC RESETX
{9, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P9_5: RFFC5072 SCLK
{9, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P9_2: RFFC5072 DATA (Bidirectional)
{13, 11, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_11: RFFC Lock Detect
{13, 14, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_14: MAX2831 CS
{13, 15, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PD_15: MAX2831 RXHP
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
{14, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PE_1: MAX2831 !SHDN
{14, 2, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
{6, 3, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
{map_aa_en.scu_port, map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = map_aa_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = map_rf5072_mix_en.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
{6, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
#else
{5, 3, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_ENX
@@ -594,9 +594,11 @@ const PALConfig pal_default_config = {
}};
#ifndef PRALINE
/* Additional GPIO configuration for HackRF OG */
static const std::array<gpio_setup_t, 6> gpio_setup_og{{
{
// GPIO0
.data = (0 << 9) // P1_2: 10K PD, BOOT1
| (1 << 8) // P1_1: 10K PU, BOOT0
@@ -611,31 +613,32 @@ static const std::array<gpio_setup_t, 6> gpio_setup_og{{
.dir = 0},
{
// GPIO2
.data = (1 << 9) // P5_0: !VAA_ENABLE
| (0 << 4) // P4_4: TXENABLE
.data = boot_bit(og_VAA_en, 1) // P5_0: !VAA_ENABLE
| (0 << 4) // P4_4: TXENABLE
,
.dir = (1 << 9) // P5_0: !VAA_ENABLE
| (1 << 4) // P4_4: TXENABLE
.dir = boot_bit(og_VAA_en, 1) // P5_0: !VAA_ENABLE
| (1 << 4) // P4_4: TXENABLE
},
{
// GPIO3
.data = (0 << 6) // P6_10: EN1V8, 10K PD
.data = boot_bit(og_1v8_en, 0) // P6_10: EN1V8, 10K PD
,
.dir = (1 << 6) // P6_10: EN1V8, 10K PD
.dir = boot_bit(og_1v8_en, 1) // P6_10: EN1V8, 10K PD
},
{// GPIO4
.data = 0,
.dir = 0},
{
// GPIO5
.data = (0 << 15) // P6_7: TX
| (0 << 12) // P4_8: SGPIO13, HOST_SYNC_EN
| (1 << 5) // P2_5: RX
.data = (0 << 15) // P6_7: TX
| boot_bit(sgpio_13, 0) // P4_8: SGPIO13, HOST_SYNC_EN
| (1 << 5) // P2_5: RX
,
.dir = (1 << 15) // P6_7: TX
| (0 << 12) // P4_8: SGPIO13, HOST_SYNC_EN
| (1 << 5) // P2_5: RX
.dir = (1 << 15) // P6_7: TX
| boot_bit(sgpio_13, 0) // P4_8: SGPIO13, HOST_SYNC_EN
| (1 << 5) // P2_5: RX
},
}};
/* Additional GPIO configuration for HackRF r9 */
@@ -655,17 +658,17 @@ static const std::array<gpio_setup_t, 6> gpio_setup_r9{{
.dir = 0},
{
// GPIO2
.data = (1 << 9) // P5_0: EN1V8, 10K PD
| (1 << 4) // P4_4: !ANT_BIAS
.data = boot_bit(r9_1v8_en, 0) // P5_0: EN1V8, 10K PD
| (1 << 4) // P4_4: !ANT_BIAS
,
.dir = (1 << 9) // P5_0: EN1V8, 10K PD
| (1 << 4) // P4_4: !ANT_BIAS
.dir = boot_bit(r9_1v8_en, 1) // P5_0: EN1V8, 10K PD
| (1 << 4) // P4_4: !ANT_BIAS
},
{
// GPIO3
.data = (1 << 6) // P6_10: !VAA_ENABLE
.data = boot_bit(r9_VAA_en, 1) // P6_10: !VAA_ENABLE
,
.dir = (1 << 6) // P6_10: !VAA_ENABLE
.dir = boot_bit(r9_VAA_en, 1) // P6_10: !VAA_ENABLE
},
{// GPIO4
.data = 0,
@@ -684,9 +687,10 @@ static const std::array<gpio_setup_t, 6> gpio_setup_r9{{
/* Additional SCU configuration for HackRF OG */
static const std::array<scu_setup_t, 9> pins_setup_og{{
/* Power control */
{5, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
{6, 10, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* EN1V8/P70: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
{map_og_VAA_en.scu_port, map_og_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_og_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
{map_og_1v8_en.scu_port, map_og_1v8_en.scu_pin, scu_config_normal_drive_t{.mode = map_og_1v8_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* EN1V8/P70: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
/* Radio section control */
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* RX/P43: U7.VCTL1(I), U10.VCTL1(I), U2.VCTL1(I) */
@@ -694,19 +698,19 @@ static const std::array<scu_setup_t, 9> pins_setup_og{{
{6, 7, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* TX/P42: U7.VCTL2(I), U10.VCTL2(I), U2.VCTL2(I) */
/* SGPIO for sample transfer interface to HackRF CPLD. */
{4, 8, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* SGPIO13/BANK2F3M2: CPLD.90/HOST_SYNC_EN(I) */
{map_sgpio_13.scu_port, map_sgpio_13.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_13.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* SGPIO13/BANK2F3M2: CPLD.90/HOST_SYNC_EN(I) */
/* Miscellaneous */
{1, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* P1_1/P74: 10K PU, BOOT0 */
{1, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* P1_2/P73: 10K PD, BOOT1 */
{2, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* ISP: 10K PU, Unused */
}};
/* Additional SCU configuration for HackRF r9 */
static const std::array<scu_setup_t, 9> pins_setup_r9{{
/* Power control */
{6, 10, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
{5, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* EN1V8: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
{map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
{map_r9_1v8_en.scu_port, map_r9_1v8_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_1v8_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* EN1V8: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
/* Radio section control */
{2, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* RX/ISP/P96: U7.VCTL(I), U10.VCTL(I), U2.VCTL(I) */
@@ -723,6 +727,7 @@ static const std::array<scu_setup_t, 9> pins_setup_r9{{
/* Miscellaneous */
{4, 8, scu_config_normal_drive_t{.mode = 1, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* CLKIN_DETECT: U26.2Y(O) */
}};
#endif // #ifndef PRALINE
#endif
@@ -904,10 +909,10 @@ extern "C" void __early_init(void) {
if ((SCB->CPUID & CORTEX_M4_CPUID_MASK) == CORTEX_M4_CPUID) {
/* Enable unaligned exception handler */
SCB_CCR |= (1 << 3);
SCB->CCR |= (1 << 3);
/* Enable MemManage, BusFault, UsageFault exception handlers */
SCB_SHCSR |= (1 << 18) | (1 << 17) | (1 << 16);
SCB->SHCSR |= (1 << 18) | (1 << 17) | (1 << 16);
/* "The reset delay is counted in IRC clock cycles. If the core frequency
* CCLK is much higher than the IRC frequency, add a software delay of
@@ -1001,8 +1006,7 @@ extern "C" void boardInit(void) {
power_control::aux_power_on();
LPC_GPIO->SET[2] = (1 << 1) | (1 << 2) | (1 << 8);
LPC_GPIO->CLR[4] = (1 << 6);
led_mcu.setActive();
#else
firmware/common/gpio.cpp
+16 -22
View File
@@ -23,6 +23,8 @@
#include "platform.hpp"
using namespace gpio_control;
namespace power_control {
/* VAA powers:
@@ -53,7 +55,7 @@ void vaa_power_on(void) {
}
/* Latch VAA to ON state (Active LOW) */
LPC_GPIO->CLR[4] = (1 << 1);
VAA_en.setActive();
#else
if (hackrf_r9) {
@@ -104,8 +106,8 @@ void vaa_power_on(void) {
}
/* Hold !VAA_ENABLE active using a GPIO, so we can reclaim and shut down the MOTOCONPWM peripheral. */
LPC_GPIO->CLR[2] = (1 << 9); // !VAA_ENABLE
LPC_GPIO->DIR[2] |= (1 << 9);
og_VAA_en.output();
og_VAA_en.setActive();
setup_pin(pin_setup_vaa_enablex_gpio_og); // P5_0 /GPIO2[ 9]/MCOB2: !VAA_ENABLE, 10K PU
peripheral_reset(&motocon_pwm_resources.reset);
@@ -122,16 +124,13 @@ void vaa_power_off(void) {
*/
#ifdef PRALINE
/* Safe state: OFF (VAA RF is active LOW, so Set = OFF) */
LPC_GPIO->SET[4] = (1 << 1);
/* Turn OFF LED3 (TX) */
LPC_GPIO->SET[2] = (1 << 8);
VAA_en.setInactive();
#else
if (hackrf_r9) {
LPC_GPIO->W3[6] = 1; // Turn OFF VAA for r9 P6_10
r9_VAA_en.setInactive(); // Turn OFF VAA for r9 P6_10
} else {
LPC_GPIO->W2[9] = 1; // Turn OFF VAA for OG P5_0
og_VAA_en.setInactive(); // Turn OFF VAA for OG P5_0
}
#endif
}
@@ -150,34 +149,29 @@ void aux_power_off(void) {
#endif /* PRALINE */
void core_power_on(void) { // Core power enable
void core_power_on(void) {
#ifdef PRALINE
// 1.2V FPGA - P8_7 = GPIO4[7], Active HIGH (Set = ON)
LPC_GPIO->SET[4] = (1 << 7);
en_1v2.setActive();
#else
if (hackrf_r9) {
// P5_0 (GPIO2[9]) is the EN1V8 pin
LPC_GPIO->SET[2] = (1 << 9);
r9_1v8_en.setActive();
} else {
// On older OG HackRF boards, P6_10 (GPIO3[6]) is the EN1V8 pin
LPC_GPIO->SET[3] = (1 << 6);
og_1v8_en.setActive();
}
#endif
}
void core_power_off(void) { // Core power disable
void core_power_off(void) {
#ifdef PRALINE
// 1.2V FPGA - P8_7 = GPIO4[7], Active HIGH (Clear = OFF) */
LPC_GPIO->CLR[4] = (1 << 7);
en_1v2.setInactive();
#else
if (hackrf_r9) {
// P5_0 (GPIO2[9]) is the EN1V8 pin
LPC_GPIO->CLR[2] = (1 << 9);
r9_1v8_en.setInactive();
} else {
// On older OG HackRF boards, P6_10 (GPIO3[6]) is the EN1V8 pin
LPC_GPIO->CLR[3] = (1 << 6);
og_1v8_en.setInactive();
}
#endif
}
firmware/common/gpio.hpp
+221 -52
View File
@@ -28,7 +28,7 @@
#include "ch.h"
#include "hal.h"
#include "pal.h"
#include "pal_lld.h"
struct PinConfig {
const uint32_t mode;
@@ -200,6 +200,12 @@ struct Pin {
uint8_t _pin_pad;
};
// Defines the logical polarity of the GPIO pin
enum class Polarity {
ActiveHigh, // High physical state means the function is ON (default)
ActiveLow // Low physical state means the function is ON (inverted)
};
struct GPIO {
// GPIO() = delete;
// GPIO(const GPIO& gpio) = delete;
@@ -209,22 +215,15 @@ struct GPIO {
const Pin& pin,
const ioportid_t gpio_port,
const iopadid_t gpio_pad,
const uint16_t gpio_mode)
const uint16_t gpio_mode,
const Polarity polarity = Polarity::ActiveHigh) // Default parameter ensures backward compatibility
: _pin{pin},
_gpio_port{gpio_port},
_gpio_pad{gpio_pad},
_gpio_mode{gpio_mode} {
_gpio_mode{gpio_mode},
_polarity{polarity} {
}
/*
constexpr GPIO(
const GPIO& gpio
) : _pin { gpio._pin },
_gpio_port { gpio._gpio_port },
_gpio_pad { gpio._gpio_pad },
_gpio_mode { gpio._gpio_mode }
{
}
*/
constexpr ioportid_t port() const {
return _gpio_port;
}
@@ -237,6 +236,11 @@ struct GPIO {
return _pin;
}
// Returns the configured polarity of the pin
constexpr Polarity polarity() const {
return _polarity;
}
void configure() const {
_pin.mode(_gpio_mode);
}
@@ -245,6 +249,8 @@ struct GPIO {
return _gpio_mode;
}
// Physical Level Operations
void set() const {
palSetPad(_gpio_port, _gpio_pad);
}
@@ -273,6 +279,39 @@ struct GPIO {
return palReadPad(_gpio_port, _gpio_pad);
}
// Turns the feature ON based on its polarity
void setActive() const {
if (_polarity == Polarity::ActiveHigh) {
set();
} else {
clear();
}
}
// Turns the feature OFF based on its polarity
void setInactive() const {
if (_polarity == Polarity::ActiveHigh) {
clear();
} else {
set();
}
}
// Sets the logical state of the feature
void setState(const bool active) const {
if (active) {
setActive();
} else {
setInactive();
}
}
// Returns true if the feature is logically active/enabled
bool isEnabled() const {
const bool physical_state = read();
return (_polarity == Polarity::ActiveHigh) ? physical_state : !physical_state;
}
bool operator!=(const GPIO& other) const {
return (port() != other.port()) || (pad() != other.pad());
}
@@ -281,6 +320,7 @@ struct GPIO {
const ioportid_t _gpio_port;
const iopadid_t _gpio_pad;
const uint16_t _gpio_mode;
const Polarity _polarity;
};
constexpr uint32_t boot_bit(const GPIO& pin, bool state) {
@@ -306,7 +346,6 @@ inline void setup_pins(const std::array<scu_setup_t, N>& pins_setup) {
}
}
#ifdef PRALINE
namespace gpio_control {
struct PinMap {
@@ -314,55 +353,195 @@ struct PinMap {
uint8_t scu_pin;
uint8_t gpio_port;
uint8_t gpio_pad;
uint8_t gpio_mode;
};
constexpr PinMap map_p1_ctrl0{2, 10, 0, 14}; // SCU: 2, 10 | GPIO: 0, 14
constexpr PinMap map_p1_ctrl1{6, 8, 5, 16};
constexpr PinMap map_p1_ctrl2{6, 9, 3, 5};
constexpr PinMap map_p2_ctrl0{8, 3, 7, 3};
constexpr PinMap map_p2_ctrl1{8, 4, 7, 4};
constexpr PinMap map_trigger_out{2, 6, 5, 6};
constexpr PinMap map_trigger_in{13, 12, 6, 26};
#ifdef PRALINE
constexpr PinMap map_p1_ctrl0{2, 10, 0, 14, 0}; // SCU: 2, 10 | GPIO: 0, 14
constexpr PinMap map_p1_ctrl1{6, 8, 5, 16, 4};
constexpr PinMap map_p1_ctrl2{6, 9, 3, 5, 0};
constexpr PinMap map_rf5072_mix_en{9, 0, 4, 12};
constexpr PinMap map_p2_ctrl0{8, 3, 7, 3, 4};
constexpr PinMap map_p2_ctrl1{8, 4, 7, 4, 4};
constexpr PinMap map_aa_en{1, 14, 1, 7}; // Anti-Aliasing filter
constexpr PinMap map_trigger_out{2, 6, 5, 6, 4};
constexpr PinMap map_trigger_in{13, 12, 6, 26, 4};
constexpr PinMap map_clkin_ctrl{1, 20, 0, 15, 0};
constexpr PinMap map_rf5072_mix_en{9, 0, 4, 12, 0};
constexpr PinMap map_aa_en{1, 14, 1, 7, 0}; // Anti-Aliasing filter
constexpr PinMap map_sgpio_4{9, 4, 5, 17, 6};
constexpr PinMap map_sgpio_8{8, 0, 4, 0, 4};
constexpr PinMap map_sgpio_9{9, 3, 4, 15, 6};
constexpr PinMap map_sgpio_10{8, 2, 4, 2, 4};
constexpr PinMap map_en_1v2{8, 7, 4, 7, 0};
constexpr PinMap map_vregmode{4, 9, 5, 13, 4};
constexpr PinMap map_VAA_en{8, 1, 4, 1, 0};
constexpr PinMap map_led_mcu{8, 6, 4, 6, 0};
#else
constexpr PinMap map_sgpio_4{6, 3, 3, 2, 2};
constexpr PinMap map_sgpio_8{9, 6, 4, 11, 6};
constexpr PinMap map_sgpio_9{4, 3, 2, 3, 7};
constexpr PinMap map_sgpio_10{1, 14, 1, 7, 6};
constexpr PinMap map_sgpio_13{4, 8, 5, 12, 4};
constexpr PinMap map_og_1v8_en{6, 10, 3, 6, 0};
constexpr PinMap map_r9_1v8_en{5, 0, 2, 9, 0};
constexpr PinMap map_vregmode{6, 11, 3, 7, 0};
constexpr PinMap map_og_VAA_en{5, 0, 2, 9, 0};
constexpr PinMap map_r9_VAA_en{6, 10, 3, 6, 0};
#endif
constexpr PinMap map_sgpio_0{0, 0, 0, 0, 3};
constexpr PinMap map_sgpio_1{0, 1, 0, 1, 3};
constexpr PinMap map_sgpio_2{1, 15, 0, 2, 2};
constexpr PinMap map_sgpio_3{1, 16, 0, 3, 2};
constexpr PinMap map_sgpio_5{6, 6, 0, 5, 2};
constexpr PinMap map_sgpio_6{2, 2, 5, 2, 0};
constexpr PinMap map_sgpio_7{1, 0, 0, 4, 6};
constexpr PinMap map_sgpio_11{1, 17, 0, 12, 6};
constexpr PinMap map_sgpio_12{1, 18, 0, 13, 0};
constexpr PinMap map_led_usb{4, 1, 2, 1, 0};
constexpr PinMap map_led_rx{4, 2, 2, 2, 0};
constexpr PinMap map_led_tx{6, 12, 2, 8, 0};
#ifdef PRALINE
// P1 Multiplexer control pins
constexpr Pin pin_p1_ctrl0{map_p1_ctrl0.scu_port, map_p1_ctrl0.scu_pin}; // SCU: P2_10
constexpr GPIO p1_ctrl0{pin_p1_ctrl0, map_p1_ctrl0.gpio_port, map_p1_ctrl0.gpio_pad, PAL_MODE_OUTPUT_PUSHPULL}; // GPIO[0]14
constexpr Pin pin_p1_ctrl0{map_p1_ctrl0.scu_port, map_p1_ctrl0.scu_pin}; // SCU: P2_10
constexpr GPIO p1_ctrl0{pin_p1_ctrl0, map_p1_ctrl0.gpio_port, map_p1_ctrl0.gpio_pad, map_p1_ctrl0.gpio_mode}; // GPIO[0]14
constexpr Pin pin_p1_ctrl1{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin}; // SCU: P6_8
constexpr GPIO p1_ctrl1{pin_p1_ctrl1, map_p1_ctrl1.gpio_port, map_p1_ctrl1.gpio_pad, PAL_MODE_OUTPUT_PUSHPULL}; // GPIO[5]16
constexpr Pin pin_p1_ctrl1{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin}; // SCU: P6_8
constexpr GPIO p1_ctrl1{pin_p1_ctrl1, map_p1_ctrl1.gpio_port, map_p1_ctrl1.gpio_pad, map_p1_ctrl1.gpio_mode}; // GPIO[5]16
constexpr Pin pin_p1_ctrl2{map_p1_ctrl2.scu_port, map_p1_ctrl2.scu_pin}; // SCU: P6_9
constexpr GPIO p1_ctrl2{pin_p1_ctrl2, map_p1_ctrl2.gpio_port, map_p1_ctrl2.gpio_pad, PAL_MODE_OUTPUT_PUSHPULL}; // GPIO[3]5
constexpr Pin pin_p1_ctrl2{map_p1_ctrl2.scu_port, map_p1_ctrl2.scu_pin}; // SCU: P6_9
constexpr GPIO p1_ctrl2{pin_p1_ctrl2, map_p1_ctrl2.gpio_port, map_p1_ctrl2.gpio_pad, map_p1_ctrl2.gpio_mode}; // GPIO[3]5
// P2 Multiplexer control pins
constexpr Pin pin_p2_ctrl0{map_p2_ctrl0.scu_port, map_p2_ctrl0.scu_pin}; // SCU: PE_3
constexpr GPIO p2_ctrl0{pin_p2_ctrl0, map_p2_ctrl0.gpio_port, map_p2_ctrl0.gpio_pad, PAL_MODE_OUTPUT_PUSHPULL}; // GPIO[7]3
constexpr Pin pin_p2_ctrl0{map_p2_ctrl0.scu_port, map_p2_ctrl0.scu_pin}; // SCU: PE_3
constexpr GPIO p2_ctrl0{pin_p2_ctrl0, map_p2_ctrl0.gpio_port, map_p2_ctrl0.gpio_pad, map_p2_ctrl0.gpio_mode}; // GPIO[7]3
constexpr Pin pin_p2_ctrl1{map_p2_ctrl1.scu_port, map_p2_ctrl1.scu_pin}; // SCU: PE_4
constexpr GPIO p2_ctrl1{pin_p2_ctrl1, map_p2_ctrl1.gpio_port, map_p2_ctrl1.gpio_pad, PAL_MODE_OUTPUT_PUSHPULL}; // GPIO[7]4
constexpr Pin pin_p2_ctrl1{map_p2_ctrl1.scu_port, map_p2_ctrl1.scu_pin}; // SCU: PE_4
constexpr GPIO p2_ctrl1{pin_p2_ctrl1, map_p2_ctrl1.gpio_port, map_p2_ctrl1.gpio_pad, map_p2_ctrl1.gpio_mode}; // GPIO[7]4
// Trigger pins
constexpr Pin trigger_out_pin{map_trigger_out.scu_port, map_trigger_out.scu_pin}; // SCU: P2_6
constexpr GPIO trigger_out{trigger_out_pin, map_trigger_out.gpio_port, map_trigger_out.gpio_pad, PAL_MODE_OUTPUT_PUSHPULL}; // GPIO[5]6
constexpr Pin trigger_out_pin{map_trigger_out.scu_port, map_trigger_out.scu_pin}; // SCU: P2_6
constexpr GPIO trigger_out{trigger_out_pin, map_trigger_out.gpio_port, map_trigger_out.gpio_pad, map_trigger_out.gpio_mode}; // GPIO[5]6
constexpr Pin trigger_in_pin{map_trigger_in.scu_port, map_trigger_in.scu_pin}; // SCU: PD_12
constexpr GPIO trigger_in{trigger_in_pin, map_trigger_in.gpio_port, map_trigger_in.gpio_pad, PAL_MODE_INPUT}; // GPIO[6]26
constexpr Pin trigger_in_pin{map_trigger_in.scu_port, map_trigger_in.scu_pin}; // SCU: PD_12
constexpr GPIO trigger_in{trigger_in_pin, map_trigger_in.gpio_port, map_trigger_in.gpio_pad, map_trigger_in.gpio_mode}; // GPIO[6]26
// Clock input control
constexpr Pin pin_clkin_ctrl{map_clkin_ctrl.scu_port, map_clkin_ctrl.scu_pin}; // SCU: P1_20
constexpr GPIO clkin_ctrl{pin_clkin_ctrl, map_clkin_ctrl.gpio_port, map_clkin_ctrl.gpio_pad, map_clkin_ctrl.gpio_mode}; // GPIO[0]15
// RF507x
constexpr Pin pin_rf5072_mix_en{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin};
constexpr GPIO rf5072_mix_en{pin_rf5072_mix_en, map_rf5072_mix_en.gpio_port, map_rf5072_mix_en.gpio_pad, 0};
constexpr Pin pin_rf5072_mix_en{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin}; // SCU: P9_0
constexpr GPIO rf5072_mix_en{pin_rf5072_mix_en, map_rf5072_mix_en.gpio_port, map_rf5072_mix_en.gpio_pad, map_rf5072_mix_en.gpio_mode}; // GPIO[4]12
// Anti-Aliasing filter
constexpr Pin pin_aa_en{map_aa_en.scu_port, map_aa_en.scu_pin};
constexpr GPIO aa_en{pin_aa_en, map_aa_en.gpio_port, map_aa_en.gpio_pad, 0};
constexpr Pin pin_aa_en{map_aa_en.scu_port, map_aa_en.scu_pin}; // SCU: P1_14
constexpr GPIO aa_en{pin_aa_en, map_aa_en.gpio_port, map_aa_en.gpio_pad, map_aa_en.gpio_mode}; // GPIO[1]7
constexpr Pin pin_en_1v2{map_en_1v2.scu_port, map_en_1v2.scu_pin}; // SCU: P8_7
constexpr GPIO en_1v2{pin_en_1v2, map_en_1v2.gpio_port, map_en_1v2.gpio_pad, map_en_1v2.gpio_mode}; // GPIO[4]7
constexpr Pin pin_VAA_en{map_VAA_en.scu_port, map_VAA_en.scu_pin}; // SCU: P8_1
constexpr GPIO VAA_en{pin_VAA_en, map_VAA_en.gpio_port, map_VAA_en.gpio_pad, map_VAA_en.gpio_mode, Polarity::ActiveLow}; // GPIO[4]1
constexpr Pin pin_led_usb{map_led_usb.scu_port, map_led_usb.scu_pin}; // SCU: P4_1
constexpr GPIO led_usb{pin_led_usb, map_led_usb.gpio_port, map_led_usb.gpio_pad, map_led_usb.gpio_mode, Polarity::ActiveLow}; // GPIO[2]1
constexpr Pin pin_led_rx{map_led_rx.scu_port, map_led_rx.scu_pin}; // SCU: P4_2
constexpr GPIO led_rx{pin_led_rx, map_led_rx.gpio_port, map_led_rx.gpio_pad, map_led_rx.gpio_mode, Polarity::ActiveLow}; // GPIO[2]2
constexpr Pin pin_led_tx{map_led_tx.scu_port, map_led_tx.scu_pin}; // SCU: P6_12
constexpr GPIO led_tx{pin_led_tx, map_led_tx.gpio_port, map_led_tx.gpio_pad, map_led_tx.gpio_mode, Polarity::ActiveLow}; // GPIO[2]8
constexpr Pin pin_led_mcu{map_led_mcu.scu_port, map_led_mcu.scu_pin}; // SCU: P8_6
constexpr GPIO led_mcu{pin_led_mcu, map_led_mcu.gpio_port, map_led_mcu.gpio_pad, map_led_mcu.gpio_mode, Polarity::ActiveLow}; // GPIO[4]6
#else
constexpr Pin pin_sgpio_13{map_sgpio_13.scu_port, map_sgpio_13.scu_pin}; // SCU: P4_8
constexpr GPIO sgpio_13{pin_sgpio_13, map_sgpio_13.gpio_port, map_sgpio_13.gpio_pad, map_sgpio_13.gpio_mode}; // GPIO[5]12
constexpr Pin pin_og_1v8_en{map_og_1v8_en.scu_port, map_og_1v8_en.scu_pin}; // SCU: P6_10
constexpr GPIO og_1v8_en{pin_og_1v8_en, map_og_1v8_en.gpio_port, map_og_1v8_en.gpio_pad, map_og_1v8_en.gpio_mode}; // GPIO[3]6
constexpr Pin pin_r9_1v8_en{map_r9_1v8_en.scu_port, map_r9_1v8_en.scu_pin}; // SCU: P5_0
constexpr GPIO r9_1v8_en{pin_r9_1v8_en, map_r9_1v8_en.gpio_port, map_r9_1v8_en.gpio_pad, map_r9_1v8_en.gpio_mode}; // GPIO[2]9
constexpr Pin pin_og_VAA_en{map_og_VAA_en.scu_port, map_og_VAA_en.scu_pin}; // SCU: P5_0
constexpr GPIO og_VAA_en{pin_og_VAA_en, map_og_VAA_en.gpio_port, map_og_VAA_en.gpio_pad, map_og_VAA_en.gpio_mode, Polarity::ActiveLow}; // GPIO[2]9
constexpr Pin pin_r9_VAA_en{map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin}; // SCU: P6_10
constexpr GPIO r9_VAA_en{pin_r9_VAA_en, map_r9_VAA_en.gpio_port, map_r9_VAA_en.gpio_pad, map_r9_VAA_en.gpio_mode, Polarity::ActiveLow}; // GPIO[3]6
constexpr Pin pin_led_usb{map_led_usb.scu_port, map_led_usb.scu_pin}; // SCU: P4_1
constexpr GPIO led_usb{pin_led_usb, map_led_usb.gpio_port, map_led_usb.gpio_pad, map_led_usb.gpio_mode}; // GPIO[2]1
constexpr Pin pin_led_rx{map_led_rx.scu_port, map_led_rx.scu_pin}; // SCU: P4_2
constexpr GPIO led_rx{pin_led_rx, map_led_rx.gpio_port, map_led_rx.gpio_pad, map_led_rx.gpio_mode}; // GPIO[2]2
constexpr Pin pin_led_tx{map_led_tx.scu_port, map_led_tx.scu_pin}; // SCU: P6_12
constexpr GPIO led_tx{pin_led_tx, map_led_tx.gpio_port, map_led_tx.gpio_pad, map_led_tx.gpio_mode}; // GPIO[2]8
static const motocon_pwm_resources_t motocon_pwm_resources = {
.base = {.clk = &LPC_CGU->BASE_APB1_CLK, .stat = &LPC_CCU1->BASE_STAT, .stat_mask = (1 << 1)},
.branch = {.cfg = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_CFG, .stat = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_STAT},
.reset = {.output_index = 38},
};
static const scu_setup_t pin_setup_vaa_enablex_pwm = {5, 0, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
static const scu_setup_t pin_setup_vaa_enablex_gpio_og = {map_og_VAA_en.scu_port, map_og_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_og_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
static const scu_setup_t pin_setup_vaa_enablex_gpio_r9 = {map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
} // namespace gpio_control
#endif
// SGPIO
constexpr Pin pin_sgpio_0{map_sgpio_0.scu_port, map_sgpio_0.scu_pin}; // SCU: P0_0
constexpr GPIO sgpio_0{pin_sgpio_0, map_sgpio_0.gpio_port, map_sgpio_0.gpio_pad, map_sgpio_0.gpio_mode}; // GPIO[0]0
constexpr Pin pin_sgpio_1{map_sgpio_1.scu_port, map_sgpio_1.scu_pin}; // SCU: P0_1
constexpr GPIO sgpio_1{pin_sgpio_1, map_sgpio_1.gpio_port, map_sgpio_1.gpio_pad, map_sgpio_1.gpio_mode}; // GPIO[0]1
constexpr Pin pin_sgpio_2{map_sgpio_2.scu_port, map_sgpio_2.scu_pin}; // SCU: P1_15
constexpr GPIO sgpio_2{pin_sgpio_2, map_sgpio_2.gpio_port, map_sgpio_2.gpio_pad, map_sgpio_2.gpio_mode}; // GPIO[0]2
constexpr Pin pin_sgpio_3{map_sgpio_3.scu_port, map_sgpio_3.scu_pin}; // SCU: P1_16
constexpr GPIO sgpio_3{pin_sgpio_3, map_sgpio_3.gpio_port, map_sgpio_3.gpio_pad, map_sgpio_3.gpio_mode}; // GPIO[0]3
constexpr Pin pin_sgpio_4{map_sgpio_4.scu_port, map_sgpio_4.scu_pin}; // SCU: P6_3, PRALINE: P9_4
constexpr GPIO sgpio_4{pin_sgpio_4, map_sgpio_4.gpio_port, map_sgpio_4.gpio_pad, map_sgpio_4.gpio_mode}; // GPIO[6]3 PRALINE: GPIO[5]17
constexpr Pin pin_sgpio_5{map_sgpio_5.scu_port, map_sgpio_5.scu_pin}; // SCU: P6_6
constexpr GPIO sgpio_5{pin_sgpio_5, map_sgpio_5.gpio_port, map_sgpio_5.gpio_pad, map_sgpio_5.gpio_mode}; // GPIO[0]5
constexpr Pin pin_sgpio_6{map_sgpio_6.scu_port, map_sgpio_6.scu_pin}; // SCU: P2_2
constexpr GPIO sgpio_6{pin_sgpio_6, map_sgpio_6.gpio_port, map_sgpio_6.gpio_pad, map_sgpio_6.gpio_mode}; // GPIO[5]2
constexpr Pin pin_sgpio_7{map_sgpio_7.scu_port, map_sgpio_7.scu_pin}; // SCU: P1_0
constexpr GPIO sgpio_7{pin_sgpio_7, map_sgpio_7.gpio_port, map_sgpio_7.gpio_pad, map_sgpio_7.gpio_mode}; // GPIO[0]4
constexpr Pin pin_sgpio_8{map_sgpio_8.scu_port, map_sgpio_8.scu_pin}; // SCU: P9_6, PRALINE: P8_0
constexpr GPIO sgpio_8{pin_sgpio_8, map_sgpio_8.gpio_port, map_sgpio_8.gpio_pad, map_sgpio_8.gpio_mode}; // GPIO[4]11, PRALINE: GPIO[4]0
constexpr Pin pin_sgpio_9{map_sgpio_9.scu_port, map_sgpio_9.scu_pin}; // SCU: P4_3, PRALINE: P9_3
constexpr GPIO sgpio_9{pin_sgpio_9, map_sgpio_9.gpio_port, map_sgpio_9.gpio_pad, map_sgpio_9.gpio_mode}; // GPIO[2]3, PRALINE: GPIO[4]12
constexpr Pin pin_sgpio_10{map_sgpio_10.scu_port, map_sgpio_10.scu_pin}; // SCU: P1_14, PRALINE: P8_2
constexpr GPIO sgpio_10{pin_sgpio_10, map_sgpio_10.gpio_port, map_sgpio_10.gpio_pad, map_sgpio_10.gpio_mode}; // GPIO[1]7, PRALINE: GPIO[4]2
constexpr Pin pin_sgpio_11{map_sgpio_11.scu_port, map_sgpio_11.scu_pin}; // SCU: P1_17
constexpr GPIO sgpio_11{pin_sgpio_11, map_sgpio_11.gpio_port, map_sgpio_11.gpio_pad, map_sgpio_11.gpio_mode}; // GPIO[0]17
constexpr Pin pin_sgpio_12{map_sgpio_12.scu_port, map_sgpio_12.scu_pin}; // SCU: P1_18
constexpr GPIO sgpio_12{pin_sgpio_12, map_sgpio_12.gpio_port, map_sgpio_12.gpio_pad, map_sgpio_12.gpio_mode}; // GPIO[0]13
constexpr Pin pin_vregmode{map_vregmode.scu_port, map_vregmode.scu_pin}; // SCU: P6_11, PRALINE: P4_9
constexpr GPIO vregmode{pin_vregmode, map_vregmode.gpio_port, map_vregmode.gpio_pad, map_vregmode.gpio_mode}; // GPIO[3]7, PRALINE: GPIO[5]13
} // namespace gpio_control
namespace power_control {
void vaa_power_on(void);
@@ -376,16 +555,6 @@ void aux_power_off(void);
void core_power_on(void);
void core_power_off(void);
static const motocon_pwm_resources_t motocon_pwm_resources = {
.base = {.clk = &LPC_CGU->BASE_APB1_CLK, .stat = &LPC_CCU1->BASE_STAT, .stat_mask = (1 << 1)},
.branch = {.cfg = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_CFG, .stat = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_STAT},
.reset = {.output_index = 38},
};
static const scu_setup_t pin_setup_vaa_enablex_pwm = {5, 0, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
static const scu_setup_t pin_setup_vaa_enablex_gpio_og = {5, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
static const scu_setup_t pin_setup_vaa_enablex_gpio_r9 = {6, 10, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}};
} // namespace power_control
#endif /*__GPIO_H__*/
firmware/common/hackrf_gpio.hpp
+10 -49
View File
@@ -23,7 +23,6 @@
#define __HACKRF_GPIO_H__
#include "pins.hpp"
#include "led.hpp"
#include <array>
@@ -34,19 +33,11 @@ namespace one {
/* GPIO */
constexpr GPIO gpio_led_usb = gpio[GPIO2_1];
constexpr GPIO gpio_led_rx = gpio[GPIO2_2];
constexpr GPIO gpio_led_tx = gpio[GPIO2_8];
constexpr GPIO gpio_og_1v8_enable = gpio[GPIO3_6];
constexpr GPIO gpio_r9_1v8_enable = gpio[GPIO2_9];
constexpr GPIO gpio_vregmode = gpio[GPIO3_7];
constexpr GPIO gpio_rx_mix_bp = gpio[GPIO2_12];
constexpr GPIO gpio_tx_mix_bp = gpio[GPIO2_11];
#ifdef PRALINE
constexpr GPIO gpio_mix_bypass = gpio[GPIO3_2]; // P6_3: PRALINE RF path mixer bypass inverted
constexpr GPIO gpio_mix_en_n_r1_0 = gpio[GPIO5_6]; // P2_6: R1.0 board mixer bypass
constexpr GPIO gpio_mix_bypass = gpio[GPIO3_2]; // P6_3: PRALINE RF path mixer bypass inverted
// constexpr GPIO gpio_mix_en_n_r1_0 = gpio[GPIO5_6]; // P2_6: R1.0 board mixer bypass
#else
constexpr GPIO gpio_mix_bypass = gpio[GPIO5_16];
#endif
@@ -90,11 +81,11 @@ constexpr GPIO gpio_max283x_select = gpio[GPIO0_15];
#ifdef PRALINE
// PRALINE uses MAX2831 transceiver with different control pins
constexpr GPIO gpio_max283x_enable = gpio[GPIO7_1]; // MAX2831 ENABLE (PE_1)
constexpr GPIO gpio_max2831_enable = gpio[GPIO7_1]; // Alias
constexpr GPIO gpio_max283x_enable = gpio[GPIO7_1]; // MAX2831 ENABLE (PE_1)
// constexpr GPIO gpio_max2831_enable = gpio[GPIO7_1]; // Alias
constexpr GPIO gpio_max2831_rx_enable = gpio[GPIO7_2]; // MAX2831 RX_ENABLE (PE_2)
constexpr GPIO gpio_max2831_rxhp = gpio[GPIO6_29]; // MAX2831 RXHP (PD_15)
constexpr GPIO gpio_max2831_ld = gpio[GPIO4_11]; // MAX2831 Lock Detect (P9_6)
// constexpr GPIO gpio_max2831_rxhp = gpio[GPIO6_29]; // MAX2831 RXHP (PD_15)
constexpr GPIO gpio_max2831_ld = gpio[GPIO4_11]; // MAX2831 Lock Detect (P9_6)
// Legacy aliases for code compatibility
constexpr GPIO gpio_max2837_rxenable = gpio[GPIO7_2];
constexpr GPIO gpio_max2837_txenable = gpio[GPIO7_2]; // MAX2831 uses single RX/TX control
@@ -108,7 +99,6 @@ constexpr GPIO gpio_max2839_rxtx = gpio[GPIO2_5];
#ifdef PRALINE
constexpr GPIO gpio_max5864_select = gpio[GPIO6_30]; // PD_16: PRALINE MAX5864 CS
constexpr GPIO gpio_fpga_select = gpio[GPIO2_10]; // FPGA SPI CS (P5_1)
#else
constexpr GPIO gpio_max5864_select = gpio[GPIO2_7];
#endif
@@ -117,38 +107,15 @@ constexpr GPIO gpio_q_invert = gpio[GPIO0_13];
#ifdef PRALINE
// PRALINE power control
constexpr GPIO gpio_vaa_disable = gpio[GPIO4_1]; // VAA disable (P8_1)
constexpr GPIO gpio_1v2_enable = gpio[GPIO4_7]; // 1V2 enable (P8_7)
constexpr GPIO gpio_3v3aux_disable = gpio[GPIO5_15]; // 3V3 aux disable (P6_7)
constexpr GPIO gpio_3v3aux_oc = gpio[GPIO1_11]; // 3.3V aux overcurrent input (P2_11)
constexpr GPIO gpio_vbus_enable = gpio[GPIO4_4]; // VBUS_IN_EN P8_4 ->LOW
constexpr GPIO gpio_vin_enable = gpio[GPIO4_5]; // VIN_IN_EN P8_5 ->HIGH
constexpr GPIO gpio_vaa_disable = gpio[GPIO4_1]; // VAA disable (P8_1)
// PRALINE RF path control
constexpr GPIO gpio_tx_enable = gpio[GPIO3_4]; // TX enable (P6_5)
// constexpr GPIO gpio_mix_enable_n = gpio[GPIO3_2]; // Mixer enable inverted (P6_3)
constexpr GPIO gpio_tx_enable = gpio[GPIO3_4]; // TX enable (P6_5)
constexpr GPIO gpio_lpf_enable = gpio[GPIO4_8]; // LPF enable (PA_1)
constexpr GPIO gpio_rf_amp_enable = gpio[GPIO4_9]; // RF amp enable (PA_2)
constexpr GPIO gpio_ant_bias_disable = gpio[GPIO1_12]; // Antenna bias disable (P2_12)
constexpr GPIO gpio_bias_oc = gpio[GPIO3_7]; // Bias tee overcurrent input (P6_11)
// PRALINE mixer lock detect (gpio_max2831_ld defined above at line 93)
constexpr GPIO gpio_rffc5072_ld = gpio[GPIO6_25]; // Mixer lock detect (PD_11)
// PRALINE LED4
constexpr GPIO gpio_led4 = gpio[GPIO4_6]; // LED4 (P8_6)
// PRALINE dual port control
constexpr GPIO gpio_p1_ctrl0 = gpio[GPIO0_14]; // P1 control 0 (P2_10)
constexpr GPIO gpio_p1_ctrl1 = gpio[GPIO5_16]; // P1 control 1 (P6_8)
constexpr GPIO gpio_p1_ctrl2 = gpio[GPIO3_5]; // P1 control 2 (P6_9)
constexpr GPIO gpio_p2_ctrl0 = gpio[GPIO7_3]; // P2 control 0 (PE_3)
constexpr GPIO gpio_p2_ctrl1 = gpio[GPIO7_4]; // P2 control 1 (PE_4)
constexpr GPIO gpio_clkin_ctrl = gpio[GPIO0_15]; // CLKIN control (P1_20)
// PRALINE trigger/sync I/O
constexpr GPIO gpio_trigger_in = gpio[GPIO6_26]; // Trigger input (PD_12)
constexpr GPIO gpio_trigger_out = gpio[GPIO5_6]; // Trigger output (P2_6)
constexpr GPIO gpio_pps_out = gpio[GPIO5_5]; // PPS output (P2_5)
// constexpr GPIO gpio_pps_out = gpio[GPIO5_5]; // PPS output (P2_5)
#endif
@@ -170,12 +137,6 @@ constexpr GPIO gpio_r9_clkout_en = gpio[GPIO0_9];
constexpr GPIO gpio_r9_mcu_clk_en = gpio[GPIO0_8];
constexpr GPIO gpio_r9_not_ant_pwr = gpio[GPIO2_4];
/* LEDs */
constexpr LED led_usb{gpio_led_usb};
constexpr LED led_rx{gpio_led_rx};
constexpr LED led_tx{gpio_led_tx};
} /* namespace one */
} /* namespace hackrf */
firmware/common/led.hpp
-75
View File
@@ -1,75 +0,0 @@
/*
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
*
* This file is part of PortaPack.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef __LED_H__
#define __LED_H__
#include "gpio.hpp"
struct LED {
constexpr LED(const GPIO gpio)
: _gpio{gpio} {
}
void setup() const {
#ifdef PRALINE
// No-op: GPIO direction and initial OFF state are already
// enforced globally at boot by pal_default_config in board.cpp.
#else
_gpio.clear();
_gpio.output();
_gpio.configure();
#endif
}
void on() const {
#ifdef PRALINE
_gpio.clear(); /* LOW = ON for PRALINE */
#else
_gpio.set();
#endif
}
void off() const {
#ifdef PRALINE
_gpio.set(); /* HIGH = OFF for PRALINE */
#else
_gpio.clear();
#endif
}
void toggle() const {
_gpio.toggle();
}
void write(const bool value) const {
#ifdef PRALINE
_gpio.write(!value); /* Invert for PRALINE */
#else
_gpio.write(value);
#endif
}
private:
const GPIO _gpio;
};
#endif /*__LED_H__*/
hackrf
+1 -1
Submodule hackrf updated: a5fd674a9f...ba2045a866