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https://github.com/portapack-mayhem/mayhem-firmware.git
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8a16ec829cb7dc36ff20beea8a50e86d259a4456
41 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
 Totoo
|
8a16ec829c |
fix clock source change on praline (#3233)
* fix clock source change on praline * whoops |
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 Pezsma
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cafe62564e |
Gpio modify (#3229)
* Refactor GPIO configuration for PRALINE and non-PRALINE setups - Updated PinMap structure to include gpio_mode for better flexibility. - Added new GPIO mappings for SGPIO pins with appropriate configurations. - Commented out unused GPIO definitions in hackrf_gpio.hpp to improve code clarity. - Adjusted GPIO initialization for control pins to utilize the new PinMap structure. - Ensured compatibility for both PRALINE and non-PRALINE configurations by using preprocessor directives. * Refactor GPIO handling and remove LED abstraction - Updated GPIO class to support logical polarity, enabling/disabling features based on their configured state. - Replaced direct GPIO manipulation in power control functions with new GPIO methods for better readability and maintainability. - Removed the LED class and its associated functionality, as it was deemed unnecessary for the current implementation. - Adjusted GPIO initialization for various components, ensuring correct polarity settings for VAA and power enable pins. - Cleaned up unused includes and commented-out code in hackrf_gpio.hpp. * Refactor GPIO LED control methods to use setActive() and setInactive() for improved clarity * Refactor GPIO control methods to use setActive() and setInactive() for improved clarity and consistency * copilot * Update GPIO control logic and pin definitions for clarity and consistency * Refactor GPIO methods for improved naming consistency and clarity |
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Pezsma
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9ab367f2e0 |
Add praline gpio (#3218)
* Implement antenna bias control for Praline and update GPIO configurations * Add GPIO power management functions and update board initialization for Praline * Refactor power management functions for Praline and update GPIO configurations * Update GPIO configurations for Praline and enable power control pins. AA_EN enabled * Refactor GPIO configuration for Praline: update array size definitions and clean up comments * Add P1 and P2 control functions for PRALINE * Introduced P1_Function and P2_Function enums in ClockManager to manage multiplexer control. * mplemented set_p1_control and set_p2_control methods for configuring P1 and P2 control pins based on specified functions. * Updated clock_manager.hpp and clock_manager.cpp to include new functionality. * Modified MAX2837 and MAX2839 initialization to conditionally configure GPIO based on PRALINE. * Adjusted RFFC507x and RFFC507x_SPI initialization to include GPIO setup for PRALINE. - Refactored RF path initialization to remove unnecessary GPIO setup. - Updated board configuration for PRALINE to reflect new GPIO settings and pin configurations. - Cleaned up FPGA bridge code by removing unused pin configuration functions. - Adjusted SCU array size in pal_lld.h for PRALINE. - Enhanced hackrf_gpio.hpp to define multiplexer control pins for PRALINE. - Modified LED setup to accommodate active-low configuration for PRALINE. * Refactor GPIO and power control functions - Removed unused power control function declarations from board.h. - Enhanced gpio.hpp with new pin setup functions and GPIO control structures for PRALINE. - Consolidated multiplexer control pin definitions into gpio_control namespace. - Moved power control function implementations to gpio.cpp, including detailed VAA power management logic. - Updated power control functions to handle both PRALINE and HackRF R9 configurations. - Cleaned up hackrf_gpio.hpp by removing redundant multiplexer control definitions. * Refactor GPIO control for PRALINE: update MAX2831 and RFFC507x configurations, add new GPIO mappings * Refactor GPIO configurations for PRALINE: update anti-aliasing filter pin mapping, enhance LED setup logic, and add placeholder GPIO entries. * Refactor GPIO configurations for PRALINE: update LED mappings and remove unused anti-aliasing filter GPIO entry. |
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 gullradriel
|
8f5b25b10d |
PRALINE Tx and clock fix (Pr 3192 takeover (#3198) )
* fix clock init and add mayhem tx capacity * aligned external clock and RX config * fix(clock): cap TX interpolation to x16 to prevent doubled waveform speed The TX gateware only implements interpolation factors x1..x16 (tx_intrp 0..4), but the rate search could select n==5 (x32) for very low TX sample rates. That left the AFE/CLK0/CLK1 running at the x32 rate while the FPGA only interpolated by x16, clocking the TX datapath at twice the gateware output rate. Cap afe_rate and _resampling_n to the x16 limit in TX so the clocks stay aligned with the interpolation setting. * fix(praline): source PLL1 from 40MHz GP_CLKIN instead of 12MHz XTAL For the intermediate 90-110MHz PLL1 stepping stage, source PLL1 from GP_CLKIN (Si5351 CLK2/MCU_CLK at 40MHz) giving N=2, M=10, Fclk=100MHz, rather than the on-chip 12MHz XTAL bootstrap path. This matches the non-PRALINE path. Remove the dead commented-out XTAL enable/PLL code. * docs(fpga_bridge): correct register 0x03 description for PRALINE gateware Register 0x03 is RX_DIGITAL_GAIN in RX and TX_NCO_CTRL in TX, not RX_PSTEP. * Fix fpga_tx_set_nco_enable to use FPGA_REG3_TX_NCO_CTRL (0x03) |
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 qwer123
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865bdee9b3 | add external clock detect method (#3180) | ||
 stafur
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395e20d17b |
Next praline clean up (add SW: RSSI for hackrf pro praline) (#3091)
* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates. * Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A. * Cleaned up PLL A and B XTAL reference checks relative to 800 MHz. * Encapsulated HackRF Pro Praline debug and status vies into a single Pro Debug submenu as part of clean up. * Fixed BLE RX Out of Memory error. Updated LPC43xx ld scripts to accouint for additional HackRF Pro praline memory. * Addressed copilot comments for ble_rx_app by adding recent_entries_view.set_dirty. Updated ble_rx_app for easier use with heap limit set to one less than recent entries max limit. * Addressed copilot comments by updating comment clarity in source files. Updated ui_debug to allow for return reference if set for PRO debug menu item. * Improved readability of intialization parameters for the FPGA registers, and addressed 20Mhz nulls by initializing DC Notch width with standard setting, and DC Adaptiation rate with a balanced setting. * Ran format-code.sh * Added option to allow for user to set number if entries in recent list. Default is set to a relatively stable 32. * Removed #ifdef PRALINE pragmas from ble_rx_app such that HackRF One can also use the updated UI widget to allow for user to set number of entries in recent list. * Ran format-code.sh * Improved RSSI for praline. Values are now being counted correctly by statistics methods after selecting ADC = 0 0 for RSSI. This was different than for the hackrf one which uses ADC = 1. * Implemented SW RSSI calculation since HW RSSI not currently available in hackrf pro (praline) via fpga pass through. Calibrated RSSI power sensistivity to mid level signal intensitities. * In preparation for WIP allocated full 128k to M4 limiting heap for M0 to 0k, and leabing it only with 64k from bank 0. That is, bank1 and bank2 are fully allocated to M4. Cleaned up #ifdef PRALINE conditionals such taht max2837/39 are in #else conditionals, as well as continuing to clean up hackrf_r9 booleans by placing them within #else conditionals. * fix typo Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com> * Addressed co-pilot comments. Clarified use of 25 recent samples in ble app for stability, udpated comments to reflect use of avg power over pwak pwer detection, improved safety of sample packing while relying on intrinstics for execute the implementation in a single machine instruction (PKHBT) for computational and memory efficiency. |
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stafur
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9a3c2cc6ac |
Next praline clean up (fixed BLE RX crashes) (#3080)
* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates. * Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A. * Cleaned up PLL A and B XTAL reference checks relative to 800 MHz. * Encapsulated HackRF Pro Praline debug and status vies into a single Pro Debug submenu as part of clean up. * Fixed BLE RX Out of Memory error. Updated LPC43xx ld scripts to accouint for additional HackRF Pro praline memory. * Addressed copilot comments for ble_rx_app by adding recent_entries_view.set_dirty. Updated ble_rx_app for easier use with heap limit set to one less than recent entries max limit. * Addressed copilot comments by updating comment clarity in source files. Updated ui_debug to allow for return reference if set for PRO debug menu item. * Improved readability of intialization parameters for the FPGA registers, and addressed 20Mhz nulls by initializing DC Notch width with standard setting, and DC Adaptiation rate with a balanced setting. * Ran format-code.sh * Added option to allow for user to set number if entries in recent list. Default is set to a relatively stable 32. * Removed #ifdef PRALINE pragmas from ble_rx_app such that HackRF One can also use the updated UI widget to allow for user to set number of entries in recent list. * Ran format-code.sh |
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stafur
|
52239d320a |
Next praline clean up (#3077)
* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates. * Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A. * Cleaned up PLL A and B XTAL reference checks relative to 800 MHz. |
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stafur
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584587d814 |
Resolve "crackling" sounds in analog_audio_app (#3068)
* Updated PRALINE audio processing methods to account for potential slip in 25MHz reference clock. Moved all clocks to PLLB except for CLK0 to isolate the ADC from potential EMI and clock spills from the other clocks to CLK0. Added PLL reference to Clock ui_debug display and added debug view for PLLA and PLLB. Updated PRO menu in analog_audio_app to allow for 100Hz resolution in sample rate for finer control of samplerate debugging of crackling noise artifacts. Updated ppb method and set it for account for a potential 49 Hz shift in the PRALINE crystal. Started instatiating methods for synchronized DMA transfers for the spectrogram since the FFT calculations and the LCD data updates appear to be related to the crackling noise. * Added firmware/flash.h to .gitignore. * Changed reference clock for start_audio_pll to 40MHz instead of ~12MHz xtal. Moved clocks around to reflect best audio quality in analog_audio_app at 3.072 MHz sample frequency. * Ran format-code.sh. * Removed ppb in set_sampling_frequency since it created aliasing in analog_audio_app. * Expanded baseband_bandwidth back to 1750000 after testing since audio quality was retained. * Updated comments to address copilot recommendations where acceptable. * Removed firmware/flashsize.h from .gitignore as coordinated with @gullradriel. |
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stafur
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6b663894b0 |
Addresses comments from PR #3057 (#3058)
* Addressed clock inversion and fractiona/interger states. Created ui_debug display that checks expected clock frequencies for expected 3.072 MHz sampling frequency commonly utilizaed in portapack apps. * Ran format-code.sh * Addressed comments from PR. Ran format-code.sh. Updated definition of a, b, and c in comments and introduced x, y, and z for debug display. Changed default color for P2/P3 conditional debub display for MS_DIV. Removed implied recalibration since this did not address crackling sound. |
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stafur
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b8ca356ce3 |
Addressed clock inversion and fractional/interger states for 3.072 MHz sampling rate (#3057)
* Addressed clock inversion and fractiona/interger states. Created ui_debug display that checks expected clock frequencies for expected 3.072 MHz sampling frequency commonly utilizaed in portapack apps. * Ran format-code.sh |
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stafur
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3a54b112ec | Imrpoved sound quality in analog_audio_app, and added Nyquist protection option to BBW filter for praline. (#3054) | ||
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stafur
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b013e68b17 | Sampling frequency and Receiver Model tweaks. (#3053) | ||
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stafur
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b2bf0f2459 |
Legacy Initialization, Analog Audio App, and Aliasing fixes. (#3052)
* Added PRO button to analog_audio.cpp for debugging metallic ringing sounds in Audio app. Ensured consitency to 4MHz in analog_audio.cpp * Restored blutooth after loss. * Added several sampling rates to analog_audio for testing. * Ran format-code.sh * Fixed 0x03 mode for DC/Q-INV/Q-SHFT being set at every tuning and sample rate change. This was the root cause for loss of bluetooth before. Sample rate, and frequency can now be changed without need for manually resetting DC/Q-INV/Q-SHIFT settings. Updated method for setting frequncies in praline so that we have more testing options. * Ran format-code.sh and cleaned up stale comments. * Addressed comments, and removed commented line, opting for higher register values, 5E and 5D. Added WFM Debug View to support testing demodulation ringing. * Addressed comments in PR conversation to clean comments and ensure consistency at initializtion accross updated methods and displays. * Ran format-code.sh * Set initial legacy state. Improved readability of clocking initialization settings. Updated set_sampling_frequency, and udpate_bandwidth to set decimation values in the fpga_registers to avoid aliasing in low band frequencies. * Updated clock_manager to use correct clock and clock parameters for audio pll. Ran format-code.sh. |
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stafur
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56adca3bf6 |
Resolved root cause for loss of bluetooth functionality and added more testing options (#3049)
* Added PRO button to analog_audio.cpp for debugging metallic ringing sounds in Audio app. Ensured consitency to 4MHz in analog_audio.cpp * Restored blutooth after loss. * Added several sampling rates to analog_audio for testing. * Ran format-code.sh * Fixed 0x03 mode for DC/Q-INV/Q-SHFT being set at every tuning and sample rate change. This was the root cause for loss of bluetooth before. Sample rate, and frequency can now be changed without need for manually resetting DC/Q-INV/Q-SHIFT settings. Updated method for setting frequncies in praline so that we have more testing options. * Ran format-code.sh and cleaned up stale comments. * Addressed comments, and removed commented line, opting for higher register values, 5E and 5D. Added WFM Debug View to support testing demodulation ringing. * Addressed comments in PR conversation to clean comments and ensure consistency at initializtion accross updated methods and displays. * Ran format-code.sh |
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stafur
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b09efb4d3c |
Mixer lock:: update clocks and move fpga_bridge_init to portapack.cpp (#3039)
* Updated harckrf_gpio methods to more closely reflect hackrf_usb. Added some ui debug updates to RFFC5072 Status View. * Updated tuning tables for tuning.cpp. Remnoved 15MHz lower limit in max2831.cpp since lower bandwidths don't seem to be causing lower band issues. Added more opportunities for clocks to stabalize at startup in board.cpp. Added/amended UI to help with addresssing low band tuning issues. Cleaned up stale comments in radio.cpp. * Ran format-code.sh * Updated to remove commented lines as part of clean up addressing review comments. * Fixed clock_manager.cpp configruation for praline. Praline hackrf pro should have: CLK4: 6mA, Invert RFFC5072 40MHz ref and CLK5: 4mA, Invert MAX2831 40MHz ref. Improvements should be visible in the watefall at 2.4GHz, and between 2.311 and 2.599GHz. * After reviewin clock config, updated values to reflect: CLK0 MAX5864 (ADC) 40 MHz 4mA Normal Integer Minimizes sampling jitter for SNR. CLK1 iCE40 FPGA 40 MHz 6mA Normal Integer Stable timing for the SPI bridge. CLK2 LPC43xx MCU 40 MHz 4mA Normal Integer Standard reference for MCU PLL. CLK3 SMA Port P1 10 MHz 8mA Normal Integer Cleanest square wave for Ext Ref. CLK4 RFFC5072 (Mixer) 40 MHz 6mA Inverted Integer Crucial for PLL Lock stability. CLK5 MAX2831 (TRX) 40 MHz 4mA Inverted Integer Reduces phase noise in the 2.4GHz LO. CLK6 SMA Port P2 10 MHz 8mA Normal Integer Sync output for external gear. CLK7 Reserved Off N/A N/A N/A Disabled to save power/reduce EMI. * Ran format-code.sh * Moved fpga_brdige_init to portapack.cpp. This more closely resembles how hackrf_usb starts initializes the fpga, and allows time for the clocks to stabilize and facilitate locking to support low band tuning. * Ran format-code.sh * Added ProRadio Debug display to check for / debug locking. * Moved fpga_bridge_init before radio_init in portapack.cpp * Low band can now see signals. Updated clock_manager, rffc507 and portapack.cpp to ensure fpga intialized correctly. Ensures rffc507x.cpp has correct 40MHz reference frequency, prescaler, and synth configuration. * Updated radio to add q-invert on, dc-block on, and deimation=3 (8x, for 20 -> 2.5 MHz decimation for testing cleaner low band signals. * Ran format-code.sh |
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stafur
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b197a4b1de |
Update to CLK4 and CLK5 configuration for PRALINE. (#3031)
* Updated harckrf_gpio methods to more closely reflect hackrf_usb. Added some ui debug updates to RFFC5072 Status View. * Updated tuning tables for tuning.cpp. Remnoved 15MHz lower limit in max2831.cpp since lower bandwidths don't seem to be causing lower band issues. Added more opportunities for clocks to stabalize at startup in board.cpp. Added/amended UI to help with addresssing low band tuning issues. Cleaned up stale comments in radio.cpp. * Ran format-code.sh * Updated to remove commented lines as part of clean up addressing review comments. * Fixed clock_manager.cpp configruation for praline. Praline hackrf pro should have: CLK4: 6mA, Invert RFFC5072 40MHz ref and CLK5: 4mA, Invert MAX2831 40MHz ref. Improvements should be visible in the watefall at 2.4GHz, and between 2.311 and 2.599GHz. * After reviewin clock config, updated values to reflect: CLK0 MAX5864 (ADC) 40 MHz 4mA Normal Integer Minimizes sampling jitter for SNR. CLK1 iCE40 FPGA 40 MHz 6mA Normal Integer Stable timing for the SPI bridge. CLK2 LPC43xx MCU 40 MHz 4mA Normal Integer Standard reference for MCU PLL. CLK3 SMA Port P1 10 MHz 8mA Normal Integer Cleanest square wave for Ext Ref. CLK4 RFFC5072 (Mixer) 40 MHz 6mA Inverted Integer Crucial for PLL Lock stability. CLK5 MAX2831 (TRX) 40 MHz 4mA Inverted Integer Reduces phase noise in the 2.4GHz LO. CLK6 SMA Port P2 10 MHz 8mA Normal Integer Sync output for external gear. CLK7 Reserved Off N/A N/A N/A Disabled to save power/reduce EMI. * Ran format-code.sh |
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stafur
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c31a978e6f |
Next pralinetcv9.2.1 archport (#2991)
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Fix ui addition of max2831 debug display. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. * Added UI debug display for max2831 like the rffc507x. Added Filter Band display and Mixer status to Signal Path Status debug display. * Added ability to set Q: INV, or Q:NOR in Signal Path Status Debug view for testing. Also added display entries for the FGPA Ctrl register fir debugging. * Added System Diagnostics which allows testing sample rate, q-inv, and dc blk * Corrected LP - GPIO4[8], and GPIO4[9] issue which was preventing RF Amp, and LPF from chaning state. HackRF Pro (praline) now correctly changes state of LPF and RF Amp as expected. * Corrected LP - GPIO4[8], and GPIO4[9] issue which was preventing RF Amp, and LPF from chaning state. HackRF Pro (praline) now correctly changes state of LPF and RF Amp as expected. * Added consistency for testing. * Added ui to debug whether rffc5072 is locking correctly. Also addressed rf_amp fixed in on state, such that it may now be able to be toggled in HackRF Pro praline setups. * Updated format to support automated tests. * format code * Updated rffc5072 status view in ui_debug to help with debugging. Made updated recommendtions for merge from PR comments. Made updates to ensure resetx isn't reconfigured for output in rffc507x.cpp. * Ran ./format-code.sh * Added reference comment that addresses debugging in PRALINE to detail that when the capture app was requesting 15 MHz, it matched 15100000 which resulted in the 8.5M setting. To get the actual 15M setting (22.6 MHz bandwidth), I had to force a request at least 22 MHz while debugging. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com> |
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stafur
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39424632bb |
HackRF Pro (praline) arch-port initial PR (#2958)
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com> |
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gullradriel
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7e8ad83537 |
Update clang format to 18 (#2891)
* move to clang-format-18 * clang-format-18 indendation |
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 jLynx
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3d2da9c0db |
Serial info command (#1700)
* WIP adding more info * Added source output & R9 detection * WIP * WIP * Moved hackrf back * Fixed output error |
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 Mark Thompson
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93585d846a | CLKOUT workaround for r9 boards (#1671) | ||
 Bernd Herzog
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62310ad9a9 |
Config mode (#1433)
* Allow code to run without a token * Reverted submodule change by mistake * WIP force tcxo * Added check to hide if not an R9 * Fixed comments * Updated name * Fixed crashing on TCXO switching * Fixed the reboot issue * Updated boot order * Cleaned up comments * added new recovery mode * added IO * implemented cpld mode change * whitespace change * renamed config mode * inverted logic * removed r9 dependency * added disable external tcxo option to config mode * fixed CLKIN detection for r9 * integrated tcxo setting into clock selection Co-authored-by @jLynx |
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jLynx
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033c4e9a5b |
Formatted code (#1007)
* Updated style * Updated files * fixed new line * Updated spacing * File fix WIP * Updated to clang 13 * updated comment style * Removed old comment code |
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 phil-stumpy
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66ba6442b1 | Adding support for HackRF One R9, as per https://github.com/sharebrained/portapack-hackrf/pull/187 | ||
 dqs105
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7ca322fed4 |
Added options for tuning CLKOUT freq.
- Now we have variable CLKOUT. - CLKOUT can be set between 10kHz and 60MHz. (The output signal will become mostly sine shape when reaching 50MHz.) - Click on freq setting field to change tuning step. |
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dqs105
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b15b781039 |
Added options for enabling CLKOUT.
- CLKOUT can be enabled in Radio settings and status bar. - Fixed a typo(I believe) in ui_navigation. |
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 Ziggy
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b690165da3 |
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric. * PCB: Move HackRF header P9 to B.CrtYd layer. * PCB: Change a Tg reference I missed. * PCB: Update footprints for parts with mismatched CAD->tape rotation. Adjust a few layer choice and line thickness bits. * PCB: Got cold feet, switched back to rectangular pads. * PCB: Add Eco layers to be visible and Gerber output. * PCB: Use aux origin for plotting, for tidier coordinates. * PCB: Output Gerber job file, because why not? * Schematic: Correct footprints for two reference-related components. * Schematic: Remove manfuacturer and part number for DNP component. * Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination. * PCB: Update netlist and footprints from schematic. * Netlist: Updated component values, footprints. * PCB: Nudge some components and traces to address DRC clearance violations. * PCB: Allow KiCad to update zone timestamps (again?!). * PCB: Generate *all* Gerber layers. * Schematic, PCB: Update revision to 20181025. * PCB: Adjust fab layer annotations orientation and font size. * PCB: Hide mounting hole reference designators on silk layer. * PCB: Shrink U1, U3 pads to get 0.2mm space between pads. * PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options. * PCB: Revise U1 pad shape, mask, paste, thermal drills. Clearance is improved at corner pads. * PCB: Tweak U3 for better thermal pad/drill/mask/paste design. * PCB: Change solder mask color to blue. * Schematic, PCB: Update revision to 20181029. * PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math. * Update schematic * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Clock Manager: Actually store chosen clock reference Similarly-named local was covering a member and discarding the value. * Clock Manager: Reference type which contains source, frequency. * Setup: Display reference source, frequency in frequency correction screen. * LPC43xx API: Add extern "C" for use from C++. * Use LPC43xx API for SGPIO, GPDMA, I2S initialization. * I2S: Add BASE_AUDIO_CLK management. * Add MOTOCON_PWM clock/reset structure. * Serial: Fix dumb typos. * Serial: Remove extra reference operator. * Serial: Cut-and-paste error in structure type name. * Move SCU structure from PAL to LPC43xx API. It'd be nice if I gave some thought to where code should live before I commit it. * VAA power: Move code to HackRF board file It doesn't belong in PAL. * MAX5 CPLD: Add SAMPLE and EXTEST methods. * Flash image: Change packing scheme to use flash more efficiently. Application is now a single image for both M4 bootstrap and M0. Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash). * Clock Manager: Remove PLL1 power down function. * Move and rename peripherals reset function to board module. * Remove unused peripheral/clock management. * Clock Manager: Extract switch to IRC into separate function. * Clock Manager: More explicit shutdown of clocks, clock generator. * Move initialization to board module. * ChibiOS: Rename "application" board, add "baseband" board. There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup. * Clock Manager: Remove unused crystal enable/disable code. * Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown. * Reset peripherals on app shutdown. Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state). * M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0. This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown. * Audio app: Stop audio PLL on shutdown. * M4 HAL: Make LPC43XX_M4_CLK_SRC optional. This was changing the BASE_M4_CLK when a baseband was run. * LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width. * Application board: hide the peripherals_reset function, as it isn't useful except during hardware init. * Consolidate hardware init code to some degree. ClockManager is super-overloaded and murky in its purpose. Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown. * Migrate some startup code to application board. * Si5351: Use correct methods for reset(). update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown. For similar reasons, use set_clock_control() instead of setting internal state and then using the update function. * GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader. * Change application board.c to .cpp, with required dependent changes * Board: Clean up SCU configuration code/data. * I2S: Add shutdown code and use it. * LPC43xx: Consolidate a bunch of structures that had been scattered all over. ...because I'm an undisciplined coder. * I2S: Fix ordering of branch and base clock disable. Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled. * Controls: Save and expose raw navigation wheel switch state I need to do some work on debouncing and ignoring simultaneous key presses. * Controls: Add debug view for switches state. * Controls: Ignore all key presses until all keys are released. This should address some mechanical quirks of the navigation wheel used on the PortaPack. * Clock Manager: Wait for only the necessary PLL to lock. Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL. TODO: Switching PLLs may be kind of pointless now... * CMake: Pull HackRF project from GitHub and build. * CMake: Remove commented code. * CMake: Clone HackRF via HTTPS, not SSH. * CMake: Extra pause for slow post-DFU firmware boot-up. * CMake: TODO to fix SVF/XSVF file source. * CMake: Ask HackRF hackrf_usb to make DFU binary. * Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion. * Travis-CI: Update build environment to Ubuntu xenial Previously Trusty. * Travis-CI: Incorrectly structured my request for dfu-util package. I'm soooo talented. * ldscript: Mark flash, ram with correct R/W/X flags. * ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash. * Receiver: Hide PPM adjustment if clock source is not HackRF crystal. * Documentation: Update product photos and README. * Documentation: Add TCXO feature to README description. * Application: Rearrange files to match HAVOC directory structure. * Map view in AIS (#213) * Added GeoMapView to AISRecentEntryDetailView * Added autoupdate in AIS map * Revert "Map view in AIS (#213)" This reverts commit |
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 Jared Boone
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e7c0fa394b |
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric. * PCB: Move HackRF header P9 to B.CrtYd layer. * PCB: Change a Tg reference I missed. * PCB: Update footprints for parts with mismatched CAD->tape rotation. Adjust a few layer choice and line thickness bits. * PCB: Got cold feet, switched back to rectangular pads. * PCB: Add Eco layers to be visible and Gerber output. * PCB: Use aux origin for plotting, for tidier coordinates. * PCB: Output Gerber job file, because why not? * Schematic: Correct footprints for two reference-related components. * Schematic: Remove manfuacturer and part number for DNP component. * Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination. * PCB: Update netlist and footprints from schematic. * Netlist: Updated component values, footprints. * PCB: Nudge some components and traces to address DRC clearance violations. * PCB: Allow KiCad to update zone timestamps (again?!). * PCB: Generate *all* Gerber layers. * Schematic, PCB: Update revision to 20181025. * PCB: Adjust fab layer annotations orientation and font size. * PCB: Hide mounting hole reference designators on silk layer. * PCB: Shrink U1, U3 pads to get 0.2mm space between pads. * PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options. * PCB: Revise U1 pad shape, mask, paste, thermal drills. Clearance is improved at corner pads. * PCB: Tweak U3 for better thermal pad/drill/mask/paste design. * PCB: Change solder mask color to blue. * Schematic, PCB: Update revision to 20181029. * PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math. * Update schematic * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Clock Manager: Actually store chosen clock reference Similarly-named local was covering a member and discarding the value. * Clock Manager: Reference type which contains source, frequency. * Setup: Display reference source, frequency in frequency correction screen. * LPC43xx API: Add extern "C" for use from C++. * Use LPC43xx API for SGPIO, GPDMA, I2S initialization. * I2S: Add BASE_AUDIO_CLK management. * Add MOTOCON_PWM clock/reset structure. * Serial: Fix dumb typos. * Serial: Remove extra reference operator. * Serial: Cut-and-paste error in structure type name. * Move SCU structure from PAL to LPC43xx API. It'd be nice if I gave some thought to where code should live before I commit it. * VAA power: Move code to HackRF board file It doesn't belong in PAL. * MAX5 CPLD: Add SAMPLE and EXTEST methods. * Flash image: Change packing scheme to use flash more efficiently. Application is now a single image for both M4 bootstrap and M0. Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash). * Clock Manager: Remove PLL1 power down function. * Move and rename peripherals reset function to board module. * Remove unused peripheral/clock management. * Clock Manager: Extract switch to IRC into separate function. * Clock Manager: More explicit shutdown of clocks, clock generator. * Move initialization to board module. * ChibiOS: Rename "application" board, add "baseband" board. There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup. * Clock Manager: Remove unused crystal enable/disable code. * Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown. * Reset peripherals on app shutdown. Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state). * M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0. This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown. * Audio app: Stop audio PLL on shutdown. * M4 HAL: Make LPC43XX_M4_CLK_SRC optional. This was changing the BASE_M4_CLK when a baseband was run. * LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width. * Application board: hide the peripherals_reset function, as it isn't useful except during hardware init. * Consolidate hardware init code to some degree. ClockManager is super-overloaded and murky in its purpose. Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown. * Migrate some startup code to application board. * Si5351: Use correct methods for reset(). update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown. For similar reasons, use set_clock_control() instead of setting internal state and then using the update function. * GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader. * Change application board.c to .cpp, with required dependent changes * Board: Clean up SCU configuration code/data. * I2S: Add shutdown code and use it. * LPC43xx: Consolidate a bunch of structures that had been scattered all over. ...because I'm an undisciplined coder. * I2S: Fix ordering of branch and base clock disable. Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled. * Controls: Save and expose raw navigation wheel switch state I need to do some work on debouncing and ignoring simultaneous key presses. * Controls: Add debug view for switches state. * Controls: Ignore all key presses until all keys are released. This should address some mechanical quirks of the navigation wheel used on the PortaPack. * Clock Manager: Wait for only the necessary PLL to lock. Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL. TODO: Switching PLLs may be kind of pointless now... * CMake: Pull HackRF project from GitHub and build. * CMake: Remove commented code. * CMake: Clone HackRF via HTTPS, not SSH. * CMake: Extra pause for slow post-DFU firmware boot-up. * CMake: TODO to fix SVF/XSVF file source. * CMake: Ask HackRF hackrf_usb to make DFU binary. * Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion. * Travis-CI: Update build environment to Ubuntu xenial Previously Trusty. * Travis-CI: Incorrectly structured my request for dfu-util package. I'm soooo talented. * ldscript: Mark flash, ram with correct R/W/X flags. * ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash. * Receiver: Hide PPM adjustment if clock source is not HackRF crystal. * Documentation: Update product photos and README. * Documentation: Add TCXO feature to README description. * Application: Rearrange files to match HAVOC directory structure. * Map view in AIS (#213) * Added GeoMapView to AISRecentEntryDetailView * Added autoupdate in AIS map * Revert "Map view in AIS (#213)" This reverts commit |
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 Maescool
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920b98f7c9 |
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts |
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Jared Boone
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88afee26d7 | Clock Manager: Detect Si5351 CLKIN present, measure frequency, and use if approximately 10MHz. | ||
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Jared Boone
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30f2bc4149 | Clock Manager: Add API to measure LPC43xx clock inputs against IRC oscillator. | ||
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Jared Boone
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4153995944 | CPLD: Invert GCK2 to improve ADC sample timing. | ||
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Jared Boone
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a03a72474d | Insert IDIVC into audio MCLK path, so it can be divided. | ||
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Jared Boone
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f1ca3fe5bb |
Switch RFFC5072, MAX2837 back to 40MHz reference.
Turns out the MAX2837 can't tune the necessary range when given a 50MHz reference. Oops. |
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Jared Boone
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4974774f82 | Simplify PLL math when correcting for PPM. | ||
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Jared Boone
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fe7dcdc613 |
Function to adjust clock generator XTAL PLL frequency.
Needed to switch PLLA to operate in fractional mode. |
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Jared Boone
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8797aa9758 | Stop audio PLL if shutting down GP_CLKIN clock source. | ||
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Jared Boone
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bfc73a6675 |
Move update_peripheral_clocks
Incorrect order of operations would hang execution if switching to IRC. |
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Jared Boone
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c025a2bba2 | Code to shut down ClockManager-controlled devices. | ||
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Jared Boone
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dc6fee8370 | Initial firmware commit. |