mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-21 15:09:03 +00:00
Imrpoved sound quality in analog_audio_app, and added Nyquist protection option to BBW filter for praline. (#3054)
This commit is contained in:
stafur
GitHub
@@ -574,7 +574,11 @@ void AnalogAudioView::update_modulation(ReceiverModel::Mode modulation) {
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const auto is_wideband_spectrum_mode = (modulation == ReceiverModel::Mode::SpectrumAnalysis);
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receiver_model.set_modulation(modulation);
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#ifdef PRALINE
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receiver_model.set_sampling_rate(is_wideband_spectrum_mode ? spec_bw : 3023000);
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#else
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receiver_model.set_sampling_rate(is_wideband_spectrum_mode ? spec_bw : 3072000);
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#endif
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receiver_model.set_baseband_bandwidth(is_wideband_spectrum_mode ? spec_bw / 2 : 1750000);
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receiver_model.set_hidden_offset(modulation == ReceiverModel::Mode::AMAudioFMApt ? -2200 : 0); // wefax needs to be shifted, see wefax rx app.
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@@ -750,7 +750,7 @@ void WFMAudioDebugView::refresh() {
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// === Status Summary ===
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bool sample_rate_ok = (clk0_khz >= 3000 && clk0_khz <= 3200);
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bool lpf_ok = (lpf_coarse >= 0); // 7.5 MHz minimum is technically OK
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bool lpf_ok = (lpf_coarse <= 0x0F); // check against the 4-bit max
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bool dc_ok = dc_block;
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if (sample_rate_ok && lpf_ok && dc_ok) {
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@@ -2182,6 +2182,78 @@ void SystemDiagnosticsView::refresh() {
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}
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#endif
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#ifdef PRALINE
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PralineClockDebugView::PralineClockDebugView(NavigationView& nav)
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: View(),
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rows{
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{&t0_id, &t0_ma, &t0_mode, &t0_ph, &t0_st},
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{&t1_id, &t1_ma, &t1_mode, &t1_ph, &t1_st},
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{&t2_id, &t2_ma, &t2_mode, &t2_ph, &t2_st},
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{&t3_id, &t3_ma, &t3_mode, &t3_ph, &t3_st},
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{&t4_id, &t4_ma, &t4_mode, &t4_ph, &t4_st},
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{&t5_id, &t5_ma, &t5_mode, &t5_ph, &t5_st}} {
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add_children({&text_title, &text_lbl_pll, &text_pll_status,
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&text_lbl_afe, &text_afe_rate, &text_lbl_n, &text_n_val,
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&text_header,
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&t0_id, &t0_ma, &t0_mode, &t0_ph, &t0_st,
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&t1_id, &t1_ma, &t1_mode, &t1_ph, &t1_st,
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&t2_id, &t2_ma, &t2_mode, &t2_ph, &t2_st,
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&t3_id, &t3_ma, &t3_mode, &t3_ph, &t3_st,
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&t4_id, &t4_ma, &t4_mode, &t4_ph, &t4_st,
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&t5_id, &t5_ma, &t5_mode, &t5_ph, &t5_st,
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&button_refresh, &button_done});
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button_refresh.on_select = [this](Button&) { this->refresh(); };
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button_done.on_select = [&nav](Button&) { nav.pop(); };
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refresh();
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}
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void PralineClockDebugView::focus() {
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button_refresh.focus();
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}
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void PralineClockDebugView::refresh() {
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// 1. System Status
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uint8_t status = portapack::clock_manager.si5351_read_status();
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bool pll_a = !(status & 0x20);
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bool pll_b = !(status & 0x40);
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text_pll_status.set(std::string(pll_a ? "A:OK " : "A:ERR ") + (pll_b ? "B:OK" : "B:ERR"));
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text_pll_status.set_style((pll_a && pll_b) ? Theme::getInstance()->fg_green : Theme::getInstance()->fg_red);
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// 2. AFE & Decimation Info
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uint32_t base_rate = portapack::clock_manager.get_sampling_frequency();
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uint8_t n = portapack::clock_manager.get_resampling_n();
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text_afe_rate.set(to_string_dec_uint(base_rate << n) + " Hz");
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text_n_val.set(to_string_dec_uint(n));
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// 3. Clock Table Decoding
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uint8_t output_en = portapack::clock_manager.si5351_read_register(3);
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const char* ma_lookup[] = {"2m", "4m", "6m", "8m"};
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for (size_t i = 0; i < 6; i++) {
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uint8_t ctrl = portapack::clock_manager.si5351_read_register(16 + i);
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// mA (Bits 1:0)
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rows[i].ma->set(ma_lookup[ctrl & 0x03]);
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// Mode (Bit 6: 1=Integer, 0=Fractional)
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rows[i].mode->set((ctrl & 0x40) ? "INT" : "FRAC");
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rows[i].mode->set_style((ctrl & 0x40) ? Theme::getInstance()->fg_blue : Theme::getInstance()->fg_yellow);
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// Phase (Bit 4: 1=Inverted, 0=Normal)
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// Use 0x10 (Bit 4)
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rows[i].phase->set((ctrl & 0x10) ? "INVRT" : "NORM ");
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rows[i].phase->set_style((ctrl & 0x10) ? Theme::getInstance()->fg_orange : Theme::getInstance()->fg_light);
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// Status (Powered On and Output Enabled)
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bool is_on = !(ctrl & 0x80) && !(output_en & (1 << i));
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rows[i].stat->set(is_on ? "ON" : "OFF");
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rows[i].stat->set_style(is_on ? Theme::getInstance()->fg_green : Theme::getInstance()->fg_red);
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}
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}
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#endif
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#ifdef PRALINE
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/* GPIODebugView *************************************************/
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GPIODebugView::GPIODebugView(NavigationView& nav) {
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@@ -3003,6 +3075,7 @@ void DebugMenuView::on_populate() {
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add_items({
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#ifdef PRALINE
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{"System Diag", ui::Theme::getInstance()->fg_yellow->foreground, &bitmap_icon_peripherals, [this]() { nav_.push<SystemDiagnosticsView>(); }},
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{"PRO Clocks", ui::Theme::getInstance()->fg_yellow->foreground, &bitmap_icon_peripherals, [this]() { nav_.push<ui::PralineClockDebugView>(); }},
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{"Radio Diag", ui::Theme::getInstance()->fg_yellow->foreground, &bitmap_icon_peripherals, [this]() { nav_.push<RadioDiagnosticsView>(); }},
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{"WFM Audio", ui::Theme::getInstance()->fg_yellow->foreground, &bitmap_icon_peripherals, [this]() { nav_.push<WFMAudioDebugView>(); }},
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{"ProRadio Debug", ui::Theme::getInstance()->fg_yellow->foreground, &bitmap_icon_peripherals, [this]() { nav_.push<PralineRadioDebugView>(); }},
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@@ -1125,6 +1125,79 @@ class SystemDiagnosticsView : public View {
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};
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#endif
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#ifdef PRALINE
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class PralineClockDebugView : public View {
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public:
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PralineClockDebugView(NavigationView& nav);
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void focus() override;
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std::string title() const override { return "Pro Clock Status"; };
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private:
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void refresh();
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Text text_title{{0, 0, 240, 16}, "=== Pro Clock Dashboard ==="};
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// System Status
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Text text_lbl_pll{{0, 20, 80, 16}, "PLL Lock:"};
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Text text_pll_status{{88, 20, 152, 16}, "---"};
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Text text_lbl_afe{{0, 36, 80, 16}, "AFE Rate:"};
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Text text_afe_rate{{88, 36, 152, 16}, "---"};
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Text text_lbl_n{{0, 52, 80, 16}, "Decim (n):"};
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Text text_n_val{{88, 52, 152, 16}, "-"};
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// Table Header
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Text text_header{{0, 72, 240, 16}, "ID mA Mode Phase Stat"};
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// Helper structure to group row widgets for CLK0-CLK5
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struct ClockRow {
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Text* id;
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Text* ma;
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Text* mode;
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Text* phase;
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Text* stat;
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};
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std::vector<ClockRow> rows;
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// We define the actual widgets for 6 clocks
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// Note: Layout uses 16px vertical spacing per row
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Text t0_id{{0, 88, 24, 16}, "C0:"};
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Text t0_ma{{32, 88, 24, 16}, "-"};
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Text t0_mode{{64, 88, 48, 16}, "-"};
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Text t0_ph{{128, 88, 56, 16}, "-"};
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Text t0_st{{192, 88, 48, 16}, "-"};
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Text t1_id{{0, 104, 24, 16}, "C1:"};
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Text t1_ma{{32, 104, 24, 16}, "-"};
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Text t1_mode{{64, 104, 48, 16}, "-"};
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Text t1_ph{{128, 104, 56, 16}, "-"};
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Text t1_st{{192, 104, 48, 16}, "-"};
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Text t2_id{{0, 120, 24, 16}, "C2:"};
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Text t2_ma{{32, 120, 24, 16}, "-"};
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Text t2_mode{{64, 120, 48, 16}, "-"};
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Text t2_ph{{128, 120, 56, 16}, "-"};
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Text t2_st{{192, 120, 48, 16}, "-"};
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Text t3_id{{0, 136, 24, 16}, "C3:"};
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Text t3_ma{{32, 136, 24, 16}, "-"};
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Text t3_mode{{64, 136, 48, 16}, "-"};
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Text t3_ph{{128, 136, 56, 16}, "-"};
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Text t3_st{{192, 136, 48, 16}, "-"};
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Text t4_id{{0, 152, 24, 16}, "C4:"};
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Text t4_ma{{32, 152, 24, 16}, "-"};
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Text t4_mode{{64, 152, 48, 16}, "-"};
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Text t4_ph{{128, 152, 56, 16}, "-"};
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Text t4_st{{192, 152, 48, 16}, "-"};
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Text t5_id{{0, 168, 24, 16}, "C5:"};
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Text t5_ma{{32, 168, 24, 16}, "-"};
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Text t5_mode{{64, 168, 48, 16}, "-"};
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Text t5_ph{{128, 168, 56, 16}, "-"};
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Text t5_st{{192, 168, 48, 16}, "-"};
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Button button_refresh{{8, 260, 100, 24}, "Refresh"};
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Button button_done{{132, 260, 100, 24}, "Done"};
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};
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#endif
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#endif
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class DebugPeripheralsMenuView : public BtnGridView {
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@@ -247,21 +247,20 @@ constexpr ClockControls si5351c_clock_control_common{{
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constexpr ClockControls si5351a_clock_control_common{{
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#ifdef PRALINE
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// CLK0: MAX5864 (ADC)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK1: SCT_CLK - iCE40 FPGA timing clock
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK2: LPC43xx MCU
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK3: CLKOUT (optional) SMA Port P1
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK4: PRALINE MAX2831 reference (40 MHz) - INVERTED per hackrf_usb, 4mA, Integer mode
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK5: PRALINE RFFC5072 reference (40 MHz) - INVERTED, 6mA, Integer mode
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// This matches HackRF One OG configuration for RFFC5072
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK6: SMA Port P2
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK0: MAX5864 (ADC) - 4mA, Inverted (Standard for Praline sync)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_On},
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// CLK1: SCT_CLK (iCE40 FPGA) - 6mA, Inverted (Fixes 30-60Hz Drumming)
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK2: LPC43xx MCU - 4mA, Normal (Must be Integer for MCU stability)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK3: CLKOUT SMA Port P1 - 8mA, Normal
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK4: MAX2831 reference (40 MHz) - Inverted (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK5: RFFC5072 reference (40 MHz) - Inverted (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK6: SMA Port P2 - 8mA, Normal
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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#else
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off},
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@@ -274,7 +273,6 @@ constexpr ClockControls si5351a_clock_control_common{{
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// CLK6: Not used
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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#endif
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// CLK7: Not used
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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@@ -469,7 +467,9 @@ void ClockManager::init_clock_generator() {
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si5351a_clock_control_common[6].ms_src(ref_pll),
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si5351a_clock_control_common[7].ms_src(ref_pll),
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}};
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clock_generator.set_clock_control(si5351_clock_control);
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// clock_generator.set_clock_control(si5351_clock_control);
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// Use single-byte writes instead of multi-byte
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clock_generator.set_clock_control_single_byte(si5351_clock_control);
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#else
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if (hackrf_r9) {
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const PLLReg pll_reg = (reference.source == ReferenceSource::Xtal)
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@@ -686,53 +686,41 @@ void ClockManager::disable_if_clocks() {
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void ClockManager::set_sampling_frequency(const uint32_t frequency) {
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#ifdef PRALINE
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/* PRALINE: CLK0=AFE_CLK runs at sample rate (VCO/divider/2)
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* CLK1=SCT_CLK runs at 2x sample rate (VCO/divider/1)
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* Reference: hackrf_core.c sample_rate_frac_set() lines 580-582
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*/
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/* PRALINE: Match HackRF USB sample_rate_frac_set()
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* Reference: hackrf_usb radio.c lines 29-91, hackrf_core.c lines 501-685 */
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_base_band_frequency = frequency; // Store frequency for StatusViews
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/*
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* PRALINE sample rate strategy from GSG hackrf_usb radio.c:
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*
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* 1. Run ADC at the highest rate possible (up to 40 MHz)
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* PRALINE sample rate strategy:
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* 1. Maximize AFE rate to push Nyquist above MAX2831's 11.6 MHz LPF minimum
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* 2. Use FPGA decimation to achieve desired output rate
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* 3. This makes the analog LPF effective at rejecting aliases
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* 4. Re-apply frequency after to reconfigure LPF bandwidth
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* 3. Ensure AFE rate is achievable by Si5351 (clean division from 800 MHz VCO)
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*/
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// 20 MHz, since GSG reference of 40MHz caused shifts at certain values.
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constexpr uint32_t MAX_AFE_RATE = 20000000;
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constexpr uint8_t MAX_N = 5; // Max decimation = 2^5 = 32
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constexpr uint32_t MAX_AFE_RATE = 40000000; // Use 40 MHz per GSG reference
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constexpr uint8_t MAX_N = 5;
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// Calculate optimal decimation factor for RX
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// Start with n=1 (minimum decimation of 2) per reference
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uint8_t n = 1;
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uint32_t afe_rate_x2 = 2 * frequency;
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_base_band_frequency = frequency;
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while ((afe_rate_x2 <= MAX_AFE_RATE) && (n < MAX_N)) {
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afe_rate_x2 <<= 1;
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uint8_t n = 0;
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uint32_t afe_rate = frequency;
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// Find the largest n where AFE rate stays within limit
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// Start at n=0 and work up
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while (n < MAX_N) {
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uint32_t next_rate = afe_rate << 1;
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if (next_rate > MAX_AFE_RATE) break;
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afe_rate = next_rate;
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n++;
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}
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// Store decimation factor for potential use elsewhere
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_resampling_n = n;
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// The actual AFE rate = frequency * 2^n
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uint32_t afe_rate = frequency << n;
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// Set FPGA RX decimation register
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fpga_debug_register_write(2, n);
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radio::invalidate_spi_config();
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// Configure Si5351 clocks
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clock_generator.set_ms_frequency(0, afe_rate * 4, si5351_vco_f, 2); // CLK0: AFE_CLK
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clock_generator.set_ms_frequency(1, afe_rate * 4, si5351_vco_f, 1); // CLK1: SCT_CLK
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// CLK0: AFE_CLK (with r_div=1 for ÷2)
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// CLK1: SCT_CLK (with r_div=0 for ÷1, runs at 2× AFE for FPGA timing)
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clock_generator.set_ms_frequency(0, afe_rate * 2, si5351_vco_f, 1);
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clock_generator.set_ms_frequency(1, afe_rate * 2, si5351_vco_f, 0);
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#else
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/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
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* twice the frequency, and derived from the MS0 synth. So it's only
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@@ -373,6 +373,16 @@ class Si5351 {
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#endif
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}
|
||||
|
||||
#ifdef PRALINE
|
||||
void set_clock_control_single_byte(const ClockControls& clock_control) {
|
||||
_clock_control = clock_control;
|
||||
// Use single-byte writes for PRALINE (multi-byte I2C fails)
|
||||
for (size_t i = 0; i < 8; i++) {
|
||||
write_register(Register::CLKControl_Base + i, _clock_control[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool plla_loss_of_signal() {
|
||||
return (device_status() >> 5) & 1;
|
||||
}
|
||||
|
||||
@@ -589,25 +589,6 @@ init_status_t init() {
|
||||
|
||||
clock_manager.init_clock_generator();
|
||||
|
||||
#ifdef PRALINE
|
||||
// Force CLK4/CLK5 configuration BEFORE I2C bus stops
|
||||
// This ensures the inversion bits are written while I2C is still active
|
||||
|
||||
// CLK4 (MAX2831): ON, Integer, PLLA, INVERTED, MS_Self, 4mA = 0x5D
|
||||
clock_manager.si5351_write_register(20, 0x5D);
|
||||
|
||||
// CLK5 (RFFC5072): ON, Integer, PLLA, INVERTED, MS_Self, 6mA = 0x5E
|
||||
clock_manager.si5351_write_register(21, 0x5E);
|
||||
|
||||
// Enable CLK4 and CLK5 outputs NOW (before I2C stops)
|
||||
uint8_t reg3 = clock_manager.si5351_read_register(3);
|
||||
reg3 &= ~0x30; // Clear bits 4 and 5 to enable
|
||||
clock_manager.si5351_write_register(3, reg3);
|
||||
|
||||
// Wait for clocks to stabilize
|
||||
chThdSleepMilliseconds(10);
|
||||
#endif
|
||||
|
||||
i2c0.stop();
|
||||
|
||||
chThdSleepMilliseconds(10);
|
||||
|
||||
@@ -326,12 +326,23 @@ void ReceiverModel::update_baseband_bandwidth() {
|
||||
if (enabled_) {
|
||||
#ifdef PRALINE
|
||||
/*
|
||||
* PRALINE LPF bandwidth calculation from GSG hackrf_usb radio.c:
|
||||
* PRALINE LPF bandwidth calculation from GSG hackrf_usb radio.c
|
||||
*
|
||||
* Base: (sample_rate * 3) / 8
|
||||
* If quarter-shift enabled: add (AFE_rate / 8) * 2
|
||||
* The LPF should be set to capture the desired signal bandwidth
|
||||
* while the FPGA decimation filter handles anti-aliasing.
|
||||
*
|
||||
* For most modes: LPF = (output_sample_rate * 3) / 8
|
||||
* For quarter-shift: add offset for shifted spectrum
|
||||
*
|
||||
* Note: MAX2831 minimum LPF is 11.6 MHz, so for narrow sample rates
|
||||
* the hardware limit applies and FPGA filter does the real work.
|
||||
*/
|
||||
|
||||
uint32_t sample_rate = sampling_rate();
|
||||
uint8_t resampling_n = portapack::clock_manager.get_resampling_n();
|
||||
uint32_t afe_rate = sample_rate << resampling_n;
|
||||
|
||||
// Base LPF: enough to capture desired bandwidth
|
||||
uint32_t lpf_bandwidth = (sample_rate * 3) / 8;
|
||||
|
||||
// Check if quarter-shift is enabled (FPGA register 1, bits 2-3)
|
||||
@@ -339,12 +350,23 @@ void ReceiverModel::update_baseband_bandwidth() {
|
||||
uint8_t quarter_shift = (fpga_ctrl >> 2) & 0x03;
|
||||
|
||||
if (quarter_shift != 0) {
|
||||
// Get resampling factor from clock manager
|
||||
uint8_t resampling_n = portapack::clock_manager.get_resampling_n();
|
||||
uint32_t offset = (sample_rate << resampling_n) / 8; // AFE_rate / 8
|
||||
// Quarter-shift moves spectrum by AFE_rate/4, need wider LPF
|
||||
uint32_t offset = afe_rate / 8;
|
||||
lpf_bandwidth += offset * 2;
|
||||
}
|
||||
|
||||
// For best anti-alias performance, also consider AFE Nyquist
|
||||
// If our calculated LPF is below MAX2831 minimum, it doesn't matter
|
||||
// But if we can set LPF to just below AFE Nyquist, that's optimal
|
||||
uint32_t afe_nyquist = afe_rate / 2;
|
||||
|
||||
// Use the larger of: signal bandwidth requirement OR Nyquist protection
|
||||
// (but MAX2831 driver will clamp to its available settings anyway)
|
||||
if (lpf_bandwidth < afe_nyquist) {
|
||||
// Set LPF close to Nyquist for maximum alias rejection
|
||||
lpf_bandwidth = (afe_nyquist * 9) / 10; // 90% of Nyquist
|
||||
}
|
||||
|
||||
radio::set_baseband_filter_bandwidth_rx(lpf_bandwidth);
|
||||
#else
|
||||
radio::set_baseband_filter_bandwidth_rx(baseband_bandwidth());
|
||||
|
||||
Reference in New Issue
Block a user