Commit Graph

8 Commits

Author SHA1 Message Date
Ayke van Laethem b258f3424b riscv: print exception PC and code
This can be useful for debugging critical bugs in code. I haven't added
human-readable exceptions (such as "illegal instruction" or "stack
overflow") yet, they can be added when they happen in practice (to avoid
increasing code size too much).
2020-01-11 12:27:58 +01:00
Ayke van Laethem b9cdfd9e9a riscv: add bare-bones interrupt support
This commit adds support for timer interrupts, replacing the busy loop
that was used before. It is perhaps the most simple interrupt to
implement and should serve as the basis for further interrupt support in
RISC-V.
2020-01-10 08:04:13 +01:00
Ayke van Laethem ed9b2dbc03 runtime/hifive1: use CLINT peripheral for timekeeping
The CLINT is implemented both on the fe310-g002 chip and in the sifive_e
QEMU machine type. Therefore, use that peripheral for consistency.

The only difference is the clock speed, which runs at 10MHz in QEMU for
some reason instead of 32.768kHz as on the physical HiFive1 boards.
2020-01-10 08:04:13 +01:00
Ayke van Laethem 184827e4d8 riscv: support sleeping in QEMU
QEMU doesn't support the RTC peripheral yet so work around it for now.

This makes the following command work:

    tinygo run -target=hifive1-qemu ./testdata/coroutines.go
2019-12-26 09:57:58 +01:00
Ayke van Laethem 8f9419a35d targets: add hifive1-qemu for testing RISC-V bare metal in QEMU
Most tests don't pass yet, so can't add this test to the standard tests,
yet.
2019-12-07 16:47:40 +01:00
Ron Evans 2168b1b516 machine/hifive1: add GPIO Get() implementation and update other implementation to match latest SVD wrappers
Signed-off-by: Ron Evans <ron@hybridgroup.com>
2019-10-09 18:54:10 +02:00
Ayke van Laethem a04db67ea9 runtime: work around a bug in LLVM for .bss zeroing
See the following bug: https://bugs.llvm.org/show_bug.cgi?id=42881

I think this is a bug in LLVM, but the code in question wasn't the best
code anyway. By fixing this, about 16 bytes of code are saved on ARM
chips (and much more on AVR).
2019-08-05 10:07:46 +02:00
Ayke van Laethem ffa38b183b all: add HiFive1 rev B board with RISC-V architecture
This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
2019-07-07 14:03:24 +02:00