targets: add hifive1-qemu for testing RISC-V bare metal in QEMU

Most tests don't pass yet, so can't add this test to the standard tests,
yet.

src/runtime/runtime_fe310.go

@@ -9,7 +9,6 @@ import (
 	"machine"
 	"unsafe"
 
-	"device/riscv"
 	"device/sifive"
 )
 
@@ -106,10 +105,3 @@ func sleepTicks(d timeUnit) {
 	for ticks() < target {
 	}
 }
-
-func abort() {
-	// lock up forever
-	for {
-		riscv.Asm("wfi")
-	}
-}

src/runtime/runtime_fe310_baremetal.go

@@ -0,0 +1,14 @@
+// +build fe310,!qemu
+
+package runtime
+
+import (
+	"device/riscv"
+)
+
+func abort() {
+	// lock up forever
+	for {
+		riscv.Asm("wfi")
+	}
+}

src/runtime/runtime_fe310_qemu.go

@@ -0,0 +1,16 @@
+// +build fe310,qemu
+
+package runtime
+
+import (
+	"runtime/volatile"
+	"unsafe"
+)
+
+// Special memory-mapped device to exit tests, created by SiFive.
+var testExit = (*volatile.Register32)(unsafe.Pointer(uintptr(0x100000)))
+
+func abort() {
+	// Signal a successful exit.
+	testExit.Set(0x5555)
+}

targets/hifive1-qemu.json

@@ -0,0 +1,6 @@
+{
+	"inherits": ["fe310"],
+	"build-tags": ["hifive1b", "qemu"],
+	"linkerscript": "targets/hifive1-qemu.ld",
+	"emulator": ["qemu-system-riscv32", "-machine", "sifive_e", "-nographic", "-kernel"]
+}

targets/hifive1-qemu.ld

@@ -0,0 +1,13 @@
+
+/* memory map:
+ * https://github.com/sifive/freedom-e-sdk/blob/v201908-branch/bsp/sifive-hifive1/metal.default.lds
+ */
+MEMORY
+{
+    FLASH_TEXT (rw) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
+    RAM (xrw)       : ORIGIN = 0x80000000, LENGTH = 0x4000
+}
+
+_stack_size = 2K;
+
+INCLUDE "targets/riscv.ld"

targets/riscv.json

@@ -22,5 +22,6 @@
 	],
 	"extra-files": [
 		"src/device/riscv/start.S"
-	]
+	],
+	"gdb": "riscv64-unknown-elf-gdb"
 }