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ws2812: add nrf52 support, update timings for m0 and avr
This commit adds support for the nrf52, which is a Cortex-M4 running at 64MHz. While implementing this, I discovered that the timings for AVR/16MHz and Cortex-M0 at 16MHz weren't quite right. They do work, but were slightly out of spec. So I fixed this as well.
This commit is contained in:
Ayke van Laethem
committed by
Ron Evans
Ron Evans
parent
1475a63798
commit
4ff437e5d4
@@ -14,6 +14,12 @@ func (d Device) WriteByte(c byte) error {
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portSet, maskSet := d.Pin.PortMaskSet()
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portClear, maskClear := d.Pin.PortMaskClear()
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// See:
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// https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
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// T0H: 4 cycles or 250ns
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// T0L: 14 cycles or 875ns -> together 18 cycles or 1125ns
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// T1H: 9 cycles or 562ns
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// T1L: 8 cycles or 500ns -> together 17 cycles or 1062ns
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avr.AsmFull(`
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send_bit:
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st {portSet}, {maskSet} ; [2] set output high
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@@ -21,13 +27,14 @@ func (d Device) WriteByte(c byte) error {
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brcs skip_store ; [1/2] branch if this bit is high (long pulse)
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st {portClear}, {maskClear} ; [2] set output low (short pulse)
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skip_store:
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nop ; [6] wait before changing the output again
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nop
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nop
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nop ; [4] wait before changing the output again
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nop
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nop
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nop
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st {portClear}, {maskClear} ; [2] set output low (end of pulse)
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nop ; [3]
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nop
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nop
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subi {i}, 1 ; [1] subtract one (for the loop)
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brne send_bit ; [1/2] send the next bit, if not at the end of the loop
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`, map[string]interface{}{
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+15
-9
@@ -15,23 +15,29 @@ func (d Device) WriteByte(c byte) error {
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portSet, maskSet := d.Pin.PortMaskSet()
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portClear, maskClear := d.Pin.PortMaskClear()
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// See:
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// https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
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// T0H: 4 cycles or 250ns
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// T0L: 14 cycles or 875ns -> together 18 cycles or 1125ns
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// T1H: 10 cycles or 625ns
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// T1H: 8 cycles or 500ns -> together 18 cycles or 1125ns
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value := uint32(c) << 24
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arm.AsmFull(`
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send_bit:
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str {maskSet}, {portSet}
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lsls {value}, #1
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bcs.n skip_store
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str {maskClear}, {portClear}
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str {maskSet}, {portSet} @ [2] T0H and T0L start here
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lsls {value}, #1 @ [1]
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bcs.n skip_store @ [1/3]
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str {maskClear}, {portClear} @ [2] T0H -> T0L transition
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skip_store:
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nop @ [4]
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nop
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nop
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nop
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str {maskClear}, {portClear} @ [2] T1H -> T1L transition
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nop @ [2]
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nop
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nop
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nop
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str {maskClear}, {portClear}
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subs {i}, #1
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bne.n send_bit
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subs {i}, #1 @ [1]
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bne.n send_bit @ [1/3]
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`, map[string]interface{}{
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"value": value,
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"i": 8,
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@@ -0,0 +1,107 @@
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// +build nrf52
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package ws2812
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// This file implements the WS2812 protocol for 64MHz Cortex-M4
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// microcontrollers.
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import (
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"device/arm"
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)
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// Send a single byte using the WS2812 protocol.
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func (d Device) WriteByte(c byte) error {
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// For the Cortex-M4 at 64MHz
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portSet, maskSet := d.Pin.PortMaskSet()
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portClear, maskClear := d.Pin.PortMaskClear()
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// See:
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// https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
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// T0H: 14-16 cycles or 218.75ns - 250.00ns
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// T0L: 54-56 cycles or 843.75ns - 875.00ns
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// +: 68-72 cycles or 1062.50ns - 1125.00ns
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// T1H: 36-38 cycles or 562.50ns - 593.75ns
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// T1L: 30-32 cycles or 468.75ns - 500.0ns
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// +: 66-70 cycles or 1031.25ns - 1093.75ns
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// A branch is treated here as 1-3 cycles, because apparently it might get
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// speculated. This is more of a guess than hard fact, because the only docs
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// by ARM that state this are now considered superseded (by what?).
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value := uint32(c) << 24
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arm.AsmFull(`
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send_bit:
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str {maskSet}, {portSet} @ [2] T0H and T0L start here
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lsls {value}, #1 @ [1]
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nop @ [10]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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bcs.n skip_store @ [1-3]
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str {maskClear}, {portClear} @ [2] T0H -> T0L transition
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skip_store:
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nop @ [22]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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str {maskClear}, {portClear} @ [2] T1H -> T1L transition
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nop @ [26]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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subs {i}, #1 @ [1]
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bne.n send_bit @ [1-3]
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`, map[string]interface{}{
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"value": value,
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"i": 8,
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"maskSet": maskSet,
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"portSet": portSet,
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"maskClear": maskClear,
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"portClear": portClear,
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})
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return nil
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}
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