Ayke van Laethem b9cdfd9e9a riscv: add bare-bones interrupt support ...

This commit adds support for timer interrupts, replacing the busy loop
that was used before. It is perhaps the most simple interrupt to
implement and should serve as the basis for further interrupt support in
RISC-V.

2020-01-10 08:04:13 +01:00

..

csr.go

compiler,riscv: implement CSR operations as intrinsics

2020-01-10 08:04:13 +01:00

riscv.go

all: add HiFive1 rev B board with RISC-V architecture

2019-07-07 14:03:24 +02:00

start.S

riscv: add bare-bones interrupt support

2020-01-10 08:04:13 +01:00