Files
tinygo/tools/gen-py32-targets/devices.csv
T
Pavel Burgr b420a8be17 Puya PY32F MCU support (#5106)
* pinout yamls removed

* machine: implement default UART pin configuration for Embedfire boards

* flash command moved to chip level so VS Code plugin can select bare chip

* machine: add support for alternate pin mode configuration

* add build targets for embedfire on py32

* add support for embedfire target in GNUmakefile for py32

* lib/py32-svd: remove duplicate DBGMCU.IDCODE CODE field

Update submodule to fix duplicate SetIDCODE/GetIDCODE method
declarations in the generated py32f002bxx.go device file.

* update subproject commit reference in py32-svd

* refactor: update CPU frequency handling in machine and runtime packages

* refactor: replace ConfigureUARTPin function with direct pin configuration in UART setup

* SetAltFunc documentation for GPIO pin alternate functions

* refactor: improve UART write and flush error handling with timeout

* machine/py32: generalize UART driver to any USART

Add a per-instance setup func to the UART type so the driver is no longer
hardwired to USART1. DefaultUART stays USART1; add UART2 (USART2) in a
separately build-tagged file since py32f002x parts lack USART2. RX IRQ
handlers reference runtime-assigned vars to break the init cycle, and setup
is assigned in the var initializer so it runs before InitSerial.

Add the py32f003_32k_4k target (32K flash / 4K RAM).

* Add canonical PY32F002, F003, and F030 density targets

Use CMSIS/pyocd device names for target files and build tags. Add all F003 and F030 densities plus F002A/B, correct F002B to 24K flash and its own startup file, fix the F030x8 pyocd target, and update Embedfire inheritance.

* Add targets for all PY32 CMSIS devices

* Support all PY32 register layout variants

* machine/py32: use generated register definitions

* machine/py32: fix alternate-function documentation

* machine/py32: report the configured CPU frequency

* machine/py32: use unsafe.Add for GPIO ports

* machine/py32: bound and yield UART polling

* machine/py32: configure UART pins from UARTConfig

* build: use the current PY32 SVD repository URL

* test: cover PY32 UART register layouts

* machine/py32: restore dynamic CPU frequency tracking

* machine/py32: share the USART TX-ready bit

* targets/py32: scale system stacks with RAM

* machine/py32: keep clock state internal

* targets/py32: normalize generated metadata

* machine/py32: normalize GPIO configuration

* machine/py32: fix T020 UART setup

* machine/py32: reduce clock variant files

* machine/py32: clean up UART variants

* machine/py32: decouple UART clock capability

* lib/py32-svd: use organization repository

* runtime/py32: name 24MHz HSI encodings

* machine/py32: derive startup clock from capability

* machine/py32: use generated USART clock mask

* machine/py32: name T020 8-bit UART mode

* ci: include PY32 in sharded smoke tests

* runtime: remove PY32 HSI frequency workaround
2026-08-29 08:41:43 +02:00

5.4 KiB

1partfamilycoreflash_startflash_sizeram_startram_size
2py32e407xcpy32e407xxm40x080000000x400000x200000000x1c000
3py32e407xdpy32e407xxm40x080000000x600000x200000000x24000
4py32e407xepy32e407xxm40x080000000x800000x200000000x24000
5py32f001cx4py32f001cxxm00x080000000x40000x200000000xc00
6py32f002ax5py32f002axxm00x080000000x50000x200000000xc00
7py32f002bx5py32f002bxxm00x080000000x60000x200000000xc00
8py32f002cx5py32f002cxxm00x080000000x80000x200000000xc00
9py32f002xx2py32f002xxxm00x080000000x20000x200000000xc00
10py32f002xx4py32f002xxxm00x080000000x40000x200000000xc00
11py32f002xx5py32f002xxxm00x080000000x60000x200000000xc00
12py32f002zx4py32f002zxxm00x080000000x40000x200000000xc00
13py32f003x4py32f003xxm00x080000000x40000x200000000x800
14py32f003x6py32f003xxm00x080000000x80000x200000000x1000
15py32f003x7py32f003xxm00x080000000xc0000x200000000x1800
16py32f003x8py32f003xxm00x080000000x100000x200000000x2000
17py32f021x8py32f021xxm00x080000000x100000x200000000x2000
18py32f030x4py32f030xxm00x080000000x40000x200000000x800
19py32f030x6py32f030xxm00x080000000x80000x200000000x1000
20py32f030x7py32f030xxm00x080000000xc0000x200000000x1800
21py32f030x8py32f030xxm00x080000000x100000x200000000x2000
22py32f031x4py32f031xxm00x080000000x40000x200000000x800
23py32f031x6py32f031xxm00x080000000x80000x200000000x1000
24py32f031x7py32f031xxm00x080000000xc0000x200000000x1800
25py32f031x8py32f031xxm00x080000000x100000x200000000x2000
26py32f032x8py32f032xxm00x080000000x100000x200000000x2000
27py32f040cx6py32f040cxxm00x080000000x80000x200000000x1000
28py32f040cx8py32f040cxxm00x080000000x100000x200000000x2000
29py32f040cx9py32f040cxxm00x080000000x180000x200000000x3000
30py32f040cxbpy32f040cxxm00x080000000x200000x200000000x4000
31py32f040epxbpy32f040epxxm00x080000000x200000x200000000x4000
32py32f040ex6py32f040exxm00x080000000x80000x200000000x1000
33py32f040ex8py32f040exxm00x080000000x100000x200000000x2000
34py32f040ex9py32f040exxm00x080000000x180000x200000000x3000
35py32f040exbpy32f040exxm00x080000000x200000x200000000x4000
36py32f040x6py32f040xxm00x080000000x80000x200000000x1000
37py32f040x8py32f040xxm00x080000000x100000x200000000x2000
38py32f040x9py32f040xxm00x080000000x180000x200000000x3000
39py32f040xbpy32f040xxm00x080000000x200000x200000000x4000
40py32f071cx6py32f071cxxm00x080000000x80000x200000000x1000
41py32f071cx8py32f071cxxm00x080000000x100000x200000000x2000
42py32f071cx9py32f071cxxm00x080000000x180000x200000000x3000
43py32f071cxbpy32f071cxxm00x080000000x200000x200000000x4000
44py32f071ex6py32f071exxm00x080000000x80000x200000000x1000
45py32f071ex8py32f071exxm00x080000000x100000x200000000x2000
46py32f071ex9py32f071exxm00x080000000x180000x200000000x3000
47py32f071exbpy32f071exxm00x080000000x200000x200000000x4000
48py32f071x6py32f071xxm00x080000000x80000x200000000x1000
49py32f071x8py32f071xxm00x080000000x100000x200000000x2000
50py32f071x9py32f071xxm00x080000000x180000x200000000x3000
51py32f071xbpy32f071xxm00x080000000x200000x200000000x4000
52py32f072cx6py32f072cxxm00x080000000x80000x200000000x1000
53py32f072cx8py32f072cxxm00x080000000x100000x200000000x2000
54py32f072cx9py32f072cxxm00x080000000x180000x200000000x3000
55py32f072cxbpy32f072cxxm00x080000000x200000x200000000x4000
56py32f072ex6py32f072exxm00x080000000x80000x200000000x1000
57py32f072ex8py32f072exxm00x080000000x100000x200000000x2000
58py32f072ex9py32f072exxm00x080000000x180000x200000000x3000
59py32f072exbpy32f072exxm00x080000000x200000x200000000x4000
60py32f072x6py32f072xxm00x080000000x80000x200000000x1000
61py32f072x8py32f072xxm00x080000000x100000x200000000x2000
62py32f072x9py32f072xxm00x080000000x180000x200000000x3000
63py32f072xbpy32f072xxm00x080000000x200000x200000000x4000
64py32f403xbpy32f403xxm40x080000000x200000x200000000x10000
65py32f403xcpy32f403xxm40x080000000x400000x200000000x10000
66py32f403xdpy32f403xxm40x080000000x600000x200000000x10000
67py32f410xbpy32f410xxm40x080000000x200000x200000000x4000
68py32l020x5py32l020xxm00x080000000x60000x200000000xc00
69py32l090xbpy32l090xxm00x080000000x200000x200000000x4000
70py32l090xcpy32l090xxm00x080000000x400000x200000000x8000
71py32m010x5py32m010xxm00x080000000x60000x200000000xc00
72py32m020x6py32m020xxm00x080000000x80000x200000000x1000
73py32m030x8py32m030xxm00x080000000x100000x200000000x2000
74py32m031x8py32m031xxm00x080000000x100000x200000000x2000
75py32m070cxbpy32m070cxxm00x080000000x200000x200000000x4000
76py32m070xbpy32m070xxm00x080000000x200000x200000000x4000
77py32md310x8py32md310xxm00x080000000x100000x200000000x2000
78py32md320x8py32md320xxm00x080000000x100000x200000000x2000
79py32md410x8py32md410xxm00x080000000x100000x200000000x2000
80py32md420x8py32md420xxm00x080000000x100000x200000000x2000
81py32md430x8py32md430xxm00x080000000x100000x200000000x2000
82py32t020bx5py32t020xxm00x080000000x50000x200000000x800
83py32t020bx6py32t020xxm00x080000000x80000x200000000x1000
84py32t020x5py32t020xxm00x080000000x50000x200000000x800
85py32t020x6py32t020xxm00x080000000x80000x200000000x1000
86py32t090xbpy32t090xxm00x080000000x200000x200000000x4000
87py32t090xcpy32t090xxm00x080000000x400000x200000000x8000
88py32t092xcpy32t092xxm00x080000000x400000x200000000x8000