Ayke van Laethem b31d241388 riscv: use MSTATUS.MIE bit instead of MIE to disable interrupts ...

This should behave the same but is compatible with the ESP32-C3 which
lacks the MIE CSR (but does have the MSTATUS CSR).

2021-10-04 21:27:00 +02:00

..

csr.go

compiler,riscv: implement CSR operations as intrinsics

2020-01-10 08:04:13 +01:00

handleinterrupt.S

maixbit: changes according to feedback

2020-07-08 00:21:59 +02:00

riscv.go

riscv: use MSTATUS.MIE bit instead of MIE to disable interrupts

2021-10-04 21:27:00 +02:00

start.S

risc-v: disable linker relaxations during gp init

2020-07-08 01:58:12 +02:00