b31d241388
riscv: use MSTATUS.MIE bit instead of MIE to disable interrupts
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This should behave the same but is compatible with the ESP32-C3 which
lacks the MIE CSR (but does have the MSTATUS CSR).
2021-10-04 21:27:00 +02:00
7ed7e6cb11
risc-v: disable linker relaxations during gp init
2020-07-08 01:58:12 +02:00
0b94e486c1
maixbit: changes according to feedback
2020-07-08 00:21:59 +02:00
43a66b39cc
riscv: refactor assembly files to support RV64 and F extension
2020-07-08 00:21:59 +02:00
ccc604d2e0
riscv: fix offset in 64bit scheduler
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Also keep common start.S file for 64 and 32 bit architectures.
2020-07-08 00:21:59 +02:00
dfab1aa717
maixbit (uart): serial is working with echo example
2020-07-08 00:21:59 +02:00
fed433c046
compiler: add support for atomic operations
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This also implements DisableInterrupts/EnableInterrupts for RISC-V, as
those operations were needed to implement a few libcalls.
2020-05-28 15:11:46 +02:00
6389e45d99
all: replace ReadRegister with AsmFull inline assembly
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This makes AsmFull more powerful (by supporting return values) and
avoids a compiler builtin.
2020-04-29 18:25:16 +02:00
b9cdfd9e9a
riscv: add bare-bones interrupt support
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This commit adds support for timer interrupts, replacing the busy loop
that was used before. It is perhaps the most simple interrupt to
implement and should serve as the basis for further interrupt support in
RISC-V.
2020-01-10 08:04:13 +01:00
360923abbf
compiler,riscv: implement CSR operations as intrinsics
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CSR operations must be implemented in assembly. The easiest way to
implement them is with some custom intrinsics in the compiler.
2020-01-10 08:04:13 +01:00
08f01ba3ff
riscv: improve startup assembly
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Now that we've switched to LLVM 9, we don't need a workaround anymore
for the 'la' pseudo-instruction.
2019-12-24 19:00:22 +01:00
ffa38b183b
all: add HiFive1 rev B board with RISC-V architecture
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This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
2019-07-07 14:03:24 +02:00
Ayke van Laethem
Yannis Huber