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https://github.com/tinygo-org/tinygo.git
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deadprogram
0c17b918fb
Add full flash XIP support for ESP32, enabling code and read-only data to execute/load directly from flash via the MMU cache rather than consuming precious SRAM. This increases available RAM from ~328KB to effectively unlimited for code/rodata, while keeping ~121KB for the Go heap. Changes: - src/device/esp/esp32.S: Add MMU initialization in call_start_cpu0 - Call ROM bootloader mmu_init() and cache_flash_mmu_set() to map DROM/IROM - Enable flash cache via ROM Cache_Read_Enable() - Fix tinygo_scanCurrentStack to spill all register windows for GC - targets/esp32-interrupts.S: Add exception diagnostics - targets/esp32.ld: Major linker script restructure for XIP - Add DROM (4MB @ 0x3F400000) and IROM (4MB @ 0x400D0000) regions - Move .rodata to DROM, main .text to IROM (both flash-mapped) - Keep boot code, vectors, and WiFi blob IRAM sections in SRAM0 - Create WiFi arena in SRAM1 pool 7/6 (64KB @ 0x3FFF0000) - Move .bss and heap to SRAM2 (200KB @ 0x3FFAE000), avoiding ROM/MAC regions - Add _drom_flash_addr variable (patched by builder with flash offset) - targets/esp32.json: Add linker wrap flags for malloc/free and WiFi functions Signed-off-by: deadprogram <ron@hybridgroup.com>
439 lines
15 KiB
ArmAsm
439 lines
15 KiB
ArmAsm
// Xtensa interrupt/exception vector table for the ESP32.
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//
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// The ESP32 uses an Xtensa LX6 core with the windowed register ABI.
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// Interrupt vectors are placed at fixed offsets from the VECBASE special
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// register. We only handle level-1 (user) interrupts for now.
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//
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// Vector offsets (from ESP32 core-isa.h XCHAL definitions):
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// 0x000 Window overflow 4
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// 0x040 Window underflow 4
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// 0x080 Window overflow 8
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// 0x0C0 Window underflow 8
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// 0x100 Window overflow 12
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// 0x140 Window underflow 12
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// 0x180 Level-2 interrupt
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// 0x1C0 Level-3 interrupt
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// 0x200 Level-4 interrupt
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// 0x240 Level-5 interrupt
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// 0x280 Debug exception (level-6)
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// 0x2C0 NMI (level-7)
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// 0x300 Kernel exception
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// 0x340 User exception (level-1 interrupt)
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// 0x3C0 Double exception
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// PS register field definitions.
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#define PS_WOE 0x00040000
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#define PS_EXCM 0x00000010
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#define PS_INTLEVEL_MASK 0x0000000F
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// -----------------------------------------------------------------------
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// Vector table — must be aligned to 0x400 (1024 bytes).
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// -----------------------------------------------------------------------
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.section .text.exception_vectors,"ax"
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.global _vector_table
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.balign 0x400
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_vector_table:
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// -----------------------------------------------------------------------
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// Offset 0x000 — Window overflow 4
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// -----------------------------------------------------------------------
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.org _vector_table + 0x000
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_window_overflow4:
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s32e a0, a5, -16
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s32e a1, a5, -12
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s32e a2, a5, -8
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s32e a3, a5, -4
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x040 — Window underflow 4
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// -----------------------------------------------------------------------
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.org _vector_table + 0x040
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_window_underflow4:
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l32e a0, a5, -16
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l32e a1, a5, -12
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l32e a2, a5, -8
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l32e a3, a5, -4
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x080 — Window overflow 8
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// -----------------------------------------------------------------------
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.org _vector_table + 0x080
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_window_overflow8:
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s32e a0, a9, -16
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l32e a0, a1, -12
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s32e a1, a9, -12
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s32e a2, a9, -8
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s32e a3, a9, -4
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s32e a4, a0, -32
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s32e a5, a0, -28
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s32e a6, a0, -24
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s32e a7, a0, -20
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x0C0 — Window underflow 8
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// -----------------------------------------------------------------------
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.org _vector_table + 0x0C0
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_window_underflow8:
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l32e a0, a9, -16
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l32e a1, a9, -12
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l32e a2, a9, -8
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l32e a7, a1, -12
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l32e a3, a9, -4
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l32e a4, a7, -32
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l32e a5, a7, -28
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l32e a6, a7, -24
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l32e a7, a7, -20
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x100 — Window overflow 12
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// -----------------------------------------------------------------------
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.org _vector_table + 0x100
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_window_overflow12:
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s32e a0, a13, -16
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l32e a0, a1, -12
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s32e a1, a13, -12
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s32e a2, a13, -8
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s32e a3, a13, -4
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s32e a4, a0, -48
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s32e a5, a0, -44
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s32e a6, a0, -40
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s32e a7, a0, -36
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s32e a8, a0, -32
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s32e a9, a0, -28
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s32e a10, a0, -24
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s32e a11, a0, -20
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x140 — Window underflow 12
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// -----------------------------------------------------------------------
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.org _vector_table + 0x140
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_window_underflow12:
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l32e a0, a13, -16
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l32e a1, a13, -12
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l32e a2, a13, -8
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l32e a11, a1, -12
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l32e a3, a13, -4
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l32e a4, a11, -48
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l32e a5, a11, -44
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l32e a6, a11, -40
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l32e a7, a11, -36
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l32e a8, a11, -32
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l32e a9, a11, -28
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l32e a10, a11, -24
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l32e a11, a11, -20
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x180 — Level-2 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x180
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_level2_vector:
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j _level2_vector
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// -----------------------------------------------------------------------
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// Offset 0x1C0 — Level-3 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x1C0
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_level3_vector:
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j _level3_vector
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// -----------------------------------------------------------------------
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// Offset 0x200 — Level-4 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x200
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_level4_vector:
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j _level4_vector
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// -----------------------------------------------------------------------
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// Offset 0x240 — Level-5 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x240
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_level5_vector:
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j _level5_vector
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// -----------------------------------------------------------------------
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// Offset 0x280 — Debug exception / level-6 (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x280
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_debug_vector:
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j _debug_vector
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// -----------------------------------------------------------------------
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// Offset 0x2C0 — NMI / level-7 (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x2C0
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_nmi_vector:
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j _nmi_vector
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// -----------------------------------------------------------------------
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// Offset 0x300 — Kernel exception
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// Writes EXCCAUSE+EPC1 to RTC STORE regs, then triggers software reset.
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// ESP32 RTC_CNTL base = 0x3FF48000, STORE0 offset = 0x4C.
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// -----------------------------------------------------------------------
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.org _vector_table + 0x300
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_kernel_vector:
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j _handle_kernel_exc // jump to handler below table
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// -----------------------------------------------------------------------
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// Offset 0x340 — User exception / level-1 interrupt
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//
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// Save a0 and jump to the full handler below the vector table.
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// -----------------------------------------------------------------------
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.org _vector_table + 0x340
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.global _level1_vector
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_level1_vector:
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wsr a0, EXCSAVE1 // save a0 — only scratch register available
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j _handle_level1 // jump to full handler (PC-relative, no literal pool)
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// -----------------------------------------------------------------------
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// Offset 0x3C0 — Double exception (stub — halt)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x3C0
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_double_vector:
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j _double_vector // halt
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// -----------------------------------------------------------------------
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// Level-1 interrupt handler — lives outside the vector table so there
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// is no 64-byte size constraint.
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//
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// Saves the interrupted context on the current stack, clears PS.EXCM
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// (so window overflow/underflow work), calls the Go handleInterrupt
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// dispatcher, restores context, and returns via rfe.
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//
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// We call handleInterrupt via callx4 (window rotation by 4). This is
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// required because:
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// - callx0 does not set PS.CALLINC, so the Go function's "entry"
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// instruction would use whatever CALLINC the interrupted code left,
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// causing incorrect window rotation and a garbage stack pointer.
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// - callx0 puts the return address in a0 with the raw PC (0x40xxx for
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// IRAM), whose top 2 bits (01) cause retw to decrement WindowBase
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// by 1 even though nothing was incremented.
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//
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// With callx4, CALLINC is explicitly set to 1 and the return address
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// in a4 has the top 2 bits set to 01 — matching the window rotation
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// that entry performs. After retw, WindowBase is correctly restored.
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// Our a0..a3 (including a1, the frame pointer) are NOT in the callee's
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// register window (callee uses physical regs +4..+19), so a1 is
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// preserved across the call without needing EXCSAVE1.
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// -----------------------------------------------------------------------
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// Literal data for l32r (must be at a lower address than the l32r).
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.balign 4
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.LhandleInterrupt_addr:
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.word handleInterrupt
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.Lrtc_store0_addr:
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.word 0x3FF4804C
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.Lrtc_options0_addr:
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.word 0x3FF48000
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// -----------------------------------------------------------------------
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// Kernel exception handler (out-of-table).
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// Writes diagnostic info to RTC STORE regs, triggers software reset.
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// -----------------------------------------------------------------------
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_handle_kernel_exc:
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l32r a0, .Lrtc_store0_addr // a0 = 0x3FF4804C (RTC_CNTL_STORE0)
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rsr a1, EXCCAUSE
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movi a2, 0x555
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slli a2, a2, 20 // a2 = 0x55500000
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movi a3, 6
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slli a3, a3, 16 // a3 = 0x00060000
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or a2, a2, a3 // a2 = 0x55560000
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or a1, a2, a1 // a1 = 0x5556xxxx (magic + cause)
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s32i a1, a0, 0 // STORE0
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rsr a1, EPC1
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s32i a1, a0, 4 // STORE1 = EPC1
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// Trigger software system reset (preserves RTC STORE regs).
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// RTC_CNTL_OPTIONS0 = 0x3FF48000, bit 31 = SW_SYS_RST
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l32r a0, .Lrtc_options0_addr
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l32i a1, a0, 0
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movi a2, 1
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slli a2, a2, 31
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or a1, a1, a2
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s32i a1, a0, 0 // trigger reset
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1: j 1b // wait for reset
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.global _handle_level1
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_handle_level1:
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// --- allocate 96-byte exception frame on the interrupted stack ---
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// Layout (offsets from a1 after adjustment):
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// 0: a0 4: a1(orig) 8: a2 12: a3 16: a4 20: a5
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// 24: a6 28: a7 32: a8 36: a9 40: a10 44: a11
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// 48: a12 52: a13 56: a14 60: a15
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// 64: SAR 68: EPC1 72: PS
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addi a0, a1, -96 // a0 = new frame pointer
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s32i a1, a0, 4 // save original a1 (SP)
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mov a1, a0 // a1 = frame pointer
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rsr a0, EXCSAVE1 // recover original a0
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s32i a0, a1, 0 // save original a0
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// Save general registers a2..a15.
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s32i a2, a1, 8
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s32i a3, a1, 12
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s32i a4, a1, 16
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s32i a5, a1, 20
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s32i a6, a1, 24
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s32i a7, a1, 28
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s32i a8, a1, 32
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s32i a9, a1, 36
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s32i a10, a1, 40
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s32i a11, a1, 44
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s32i a12, a1, 48
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s32i a13, a1, 52
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s32i a14, a1, 56
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s32i a15, a1, 60
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// Save special registers.
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rsr a2, SAR
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s32i a2, a1, 64
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rsr a2, EPC1
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s32i a2, a1, 68
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// Clear PS.EXCM (bit 4) so window overflow/underflow exceptions work
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// during the Go call. Set PS.INTLEVEL=1 to prevent re-entry of
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// level-1 interrupts.
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rsr a2, PS
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s32i a2, a1, 72 // save PS (with EXCM=1 set by hardware)
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movi a3, ~0x1F // mask: clear INTLEVEL (bits 0-3) + EXCM (bit 4)
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and a2, a2, a3
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movi a3, 1 // INTLEVEL = 1
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or a2, a2, a3
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wsr a2, PS
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rsync
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// Check if this is an exception (not an interrupt).
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// EXCCAUSE == 4 means level-1 interrupt; anything else is an exception.
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rsr a2, EXCCAUSE
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movi a3, 4
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beq a2, a3, .Lis_interrupt
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// --- It's an exception, not an interrupt ---
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// Halt: loop forever (no user exception handler on ESP32 by default).
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j .Lexception_halt
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.Lis_interrupt:
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// Call the Go interrupt dispatcher via callx4.
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// callx4 explicitly sets PS.CALLINC=1 and puts the return address
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// (with top 2 bits = 01) in a4. After entry rotates the window by
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// 4, the callee sees: a0 = our a4 (return addr), a1 = our a5 - N.
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// We set a5 = our frame pointer so the callee gets a valid stack.
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mov a5, a1
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l32r a2, .LhandleInterrupt_addr
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callx4 a2
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// After retw, WindowBase is restored. a0..a3 are preserved because
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// they are outside the callee's register window.
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// --- restore context ---
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// Restore PS (restores EXCM=1).
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l32i a2, a1, 72
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wsr a2, PS
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rsync
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// Restore special registers.
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l32i a2, a1, 64
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wsr a2, SAR
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l32i a2, a1, 68
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wsr a2, EPC1
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// Restore general registers a15..a2.
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l32i a15, a1, 60
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l32i a14, a1, 56
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l32i a13, a1, 52
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l32i a12, a1, 48
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l32i a11, a1, 44
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l32i a10, a1, 40
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l32i a9, a1, 36
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l32i a8, a1, 32
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l32i a7, a1, 28
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l32i a6, a1, 24
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l32i a5, a1, 20
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l32i a4, a1, 16
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l32i a3, a1, 12
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l32i a2, a1, 8
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// Restore a0 and a1 (a1 must be last since it is the frame pointer).
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l32i a0, a1, 0
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l32i a1, a1, 4 // restores original SP (deallocates frame)
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rfe
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// -----------------------------------------------------------------------
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// Exception halt: dump EXCCAUSE and EPC1 over UART0, then loop forever.
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// Helps diagnose unhandled CPU exceptions (crashes) which would otherwise
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// look like a silent freeze (especially with the watchdogs disabled).
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// -----------------------------------------------------------------------
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.Lexc_uart_fifo:
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.long 0x3FF40000 // UART0 FIFO
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.Lexc_uart_stat:
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.long 0x3FF4001C // UART0 STATUS (TXFIFO_CNT bits 23:16)
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.Lexception_halt:
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// Emit marker "\nEXC " then EXCCAUSE (8 hex), ' ', EPC1 (8 hex), '\n'.
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l32r a4, .Lexc_uart_fifo
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l32r a5, .Lexc_uart_stat
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movi a6, 10 // '\n'
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call0 .Lexc_putc
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movi a6, 'E'
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call0 .Lexc_putc
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movi a6, 'X'
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call0 .Lexc_putc
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movi a6, 'C'
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call0 .Lexc_putc
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movi a6, ' '
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call0 .Lexc_putc
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rsr a7, EXCCAUSE
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call0 .Lexc_puthex
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movi a6, ' '
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call0 .Lexc_putc
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rsr a7, EPC1
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call0 .Lexc_puthex
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movi a6, ' '
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call0 .Lexc_putc
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rsr a7, EXCVADDR
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call0 .Lexc_puthex
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movi a6, ' '
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call0 .Lexc_putc
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l32i a7, a1, 0 // saved a0 (return address of faulting frame)
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call0 .Lexc_puthex
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movi a6, 10 // '\n'
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call0 .Lexc_putc
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1:
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waiti 0
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j 1b
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// Emit char in a6 (clobbers a3). a4=fifo, a5=status. Returns via a0 (call0).
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.align 4
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.Lexc_putc:
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s32i a6, a4, 0
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2: l32i a3, a5, 0
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extui a3, a3, 16, 8
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bnez a3, 2b
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ret
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// Emit 32-bit value in a7 as 8 hex chars (clobbers a6,a8,a9,a3).
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// Uses a10 as return save since call0 to .Lexc_putc clobbers a0.
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.align 4
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.Lexc_puthex:
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mov a10, a0 // save return address
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movi a9, 28 // shift
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3:
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ssr a9
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srl a8, a7
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extui a8, a8, 0, 4 // nibble
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movi a6, 10
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bge a8, a6, 4f
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addi a6, a8, '0'
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j 5f
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4: addi a6, a8, 'a' - 10
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5: call0 .Lexc_putc
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addi a9, a9, -4
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bgez a9, 3b
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mov a0, a10 // restore return address
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ret
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