Add full flash XIP support for ESP32, enabling code and read-only data to
execute/load directly from flash via the MMU cache rather than consuming
precious SRAM. This increases available RAM from ~328KB to effectively
unlimited for code/rodata, while keeping ~121KB for the Go heap.
Changes:
- src/device/esp/esp32.S: Add MMU initialization in call_start_cpu0
- Call ROM bootloader mmu_init() and cache_flash_mmu_set() to map DROM/IROM
- Enable flash cache via ROM Cache_Read_Enable()
- Fix tinygo_scanCurrentStack to spill all register windows for GC
- targets/esp32-interrupts.S: Add exception diagnostics
- targets/esp32.ld: Major linker script restructure for XIP
- Add DROM (4MB @ 0x3F400000) and IROM (4MB @ 0x400D0000) regions
- Move .rodata to DROM, main .text to IROM (both flash-mapped)
- Keep boot code, vectors, and WiFi blob IRAM sections in SRAM0
- Create WiFi arena in SRAM1 pool 7/6 (64KB @ 0x3FFF0000)
- Move .bss and heap to SRAM2 (200KB @ 0x3FFAE000), avoiding ROM/MAC regions
- Add _drom_flash_addr variable (patched by builder with flash offset)
- targets/esp32.json: Add linker wrap flags for malloc/free and WiFi functions
Signed-off-by: deadprogram <ron@hybridgroup.com>
deadprogram