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5 Commits

Author SHA1 Message Date
Ayke van Laethem 184827e4d8 riscv: support sleeping in QEMU 
QEMU doesn't support the RTC peripheral yet so work around it for now.

This makes the following command work:

    tinygo run -target=hifive1-qemu ./testdata/coroutines.go
 2019-12-26 09:57:58 +01:00
Ayke van Laethem 8f9419a35d targets: add hifive1-qemu for testing RISC-V bare metal in QEMU 
Most tests don't pass yet, so can't add this test to the standard tests,
yet.
 2019-12-07 16:47:40 +01:00
Ron Evans 2168b1b516 machine/hifive1: add GPIO Get() implementation and update other implementation to match latest SVD wrappers 
Signed-off-by: Ron Evans <ron@hybridgroup.com>
 2019-10-09 18:54:10 +02:00
Ayke van Laethem a04db67ea9 runtime: work around a bug in LLVM for .bss zeroing 
See the following bug: https://bugs.llvm.org/show_bug.cgi?id=42881

I think this is a bug in LLVM, but the code in question wasn't the best
code anyway. By fixing this, about 16 bytes of code are saved on ARM
chips (and much more on AVR).
 2019-08-05 10:07:46 +02:00
Ayke van Laethem ffa38b183b all: add HiFive1 rev B board with RISC-V architecture 
This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
 2019-07-07 14:03:24 +02:00