mirror of
https://github.com/tinygo-org/tinygo.git
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delete old can
This commit is contained in:
Patricio Whittingslow
@@ -1,711 +0,0 @@
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//go:build stm32g0b1
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package machine
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import (
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"device/stm32"
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"errors"
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"runtime/interrupt"
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"unsafe"
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)
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// FDCAN Message RAM configuration
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// STM32G0B1 SRAMCAN base address: 0x4000B400
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// Each FDCAN instance has its own message RAM area
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const (
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sramcanBase = 0x4000B400
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// Message RAM layout sizes (matching STM32 HAL)
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sramcanFLSNbr = 28 // Max. Filter List Standard Number
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sramcanFLENbr = 8 // Max. Filter List Extended Number
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sramcanRF0Nbr = 3 // RX FIFO 0 Elements Number
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sramcanRF1Nbr = 3 // RX FIFO 1 Elements Number
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sramcanTEFNbr = 3 // TX Event FIFO Elements Number
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sramcanTFQNbr = 3 // TX FIFO/Queue Elements Number
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// Element sizes in bytes
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sramcanFLSSize = 1 * 4 // Filter Standard Element Size
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sramcanFLESize = 2 * 4 // Filter Extended Element Size
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sramcanRF0Size = 18 * 4 // RX FIFO 0 Element Size (for 64-byte data)
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sramcanRF1Size = 18 * 4 // RX FIFO 1 Element Size
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sramcanTEFSize = 2 * 4 // TX Event FIFO Element Size
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sramcanTFQSize = 18 * 4 // TX FIFO/Queue Element Size
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// Start addresses (offsets from base)
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sramcanFLSSA = 0
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sramcanFLESA = sramcanFLSSA + (sramcanFLSNbr * sramcanFLSSize)
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sramcanRF0SA = sramcanFLESA + (sramcanFLENbr * sramcanFLESize)
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sramcanRF1SA = sramcanRF0SA + (sramcanRF0Nbr * sramcanRF0Size)
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sramcanTEFSA = sramcanRF1SA + (sramcanRF1Nbr * sramcanRF1Size)
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sramcanTFQSA = sramcanTEFSA + (sramcanTEFNbr * sramcanTEFSize)
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sramcanSize = sramcanTFQSA + (sramcanTFQNbr * sramcanTFQSize)
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)
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// FDCAN element masks (for parsing message RAM)
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const (
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fdcanElementMaskSTDID = 0x1FFC0000 // Standard Identifier
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fdcanElementMaskEXTID = 0x1FFFFFFF // Extended Identifier
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fdcanElementMaskRTR = 0x20000000 // Remote Transmission Request
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fdcanElementMaskXTD = 0x40000000 // Extended Identifier flag
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fdcanElementMaskESI = 0x80000000 // Error State Indicator
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fdcanElementMaskTS = 0x0000FFFF // Timestamp
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fdcanElementMaskDLC = 0x000F0000 // Data Length Code
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fdcanElementMaskBRS = 0x00100000 // Bit Rate Switch
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fdcanElementMaskFDF = 0x00200000 // FD Format
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fdcanElementMaskEFC = 0x00800000 // Event FIFO Control
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fdcanElementMaskMM = 0xFF000000 // Message Marker
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fdcanElementMaskFIDX = 0x7F000000 // Filter Index
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fdcanElementMaskANMF = 0x80000000 // Accepted Non-matching Frame
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)
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// Interrupt flags
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const (
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FDCAN_IT_RX_FIFO0_NEW_MESSAGE = 0x00000001
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FDCAN_IT_RX_FIFO0_FULL = 0x00000002
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FDCAN_IT_RX_FIFO0_MSG_LOST = 0x00000004
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FDCAN_IT_RX_FIFO1_NEW_MESSAGE = 0x00000010
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FDCAN_IT_RX_FIFO1_FULL = 0x00000020
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FDCAN_IT_RX_FIFO1_MSG_LOST = 0x00000040
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FDCAN_IT_TX_COMPLETE = 0x00000200
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FDCAN_IT_TX_ABORT_COMPLETE = 0x00000400
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FDCAN_IT_TX_FIFO_EMPTY = 0x00000800
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FDCAN_IT_BUS_OFF = 0x02000000
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FDCAN_IT_ERROR_WARNING = 0x01000000
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FDCAN_IT_ERROR_PASSIVE = 0x00800000
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)
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// FDCAN represents an FDCAN peripheral
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type FDCAN struct {
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Bus *stm32.FDCAN_Type
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TxAltFuncSelect uint8
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RxAltFuncSelect uint8
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Interrupt interrupt.Interrupt
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instance uint8
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}
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// FDCANTransferRate represents CAN bus transfer rates
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type FDCANTransferRate uint32
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const (
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FDCANTransferRate125kbps FDCANTransferRate = 125000
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FDCANTransferRate250kbps FDCANTransferRate = 250000
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FDCANTransferRate500kbps FDCANTransferRate = 500000
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FDCANTransferRate1000kbps FDCANTransferRate = 1000000
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FDCANTransferRate2000kbps FDCANTransferRate = 2000000 // FD only
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FDCANTransferRate4000kbps FDCANTransferRate = 4000000 // FD only
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)
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// FDCANMode represents the FDCAN operating mode
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type FDCANMode uint8
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const (
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FDCANModeNormal FDCANMode = 0
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FDCANModeBusMonitoring FDCANMode = 1
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FDCANModeInternalLoopback FDCANMode = 2
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FDCANModeExternalLoopback FDCANMode = 3
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)
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// FDCANConfig holds FDCAN configuration parameters
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type FDCANConfig struct {
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TransferRate FDCANTransferRate // Nominal bit rate (arbitration phase)
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TransferRateFD FDCANTransferRate // Data bit rate (data phase), must be >= TransferRate
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Mode FDCANMode
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Tx Pin
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Rx Pin
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Standby Pin // Optional standby pin for CAN transceiver (set to NoPin if not used)
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}
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// FDCANTxBufferElement represents a transmit buffer element
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type FDCANTxBufferElement struct {
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ESI bool // Error State Indicator
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XTD bool // Extended ID flag
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RTR bool // Remote Transmission Request
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ID uint32 // CAN identifier (11-bit or 29-bit)
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MM uint8 // Message Marker
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EFC bool // Event FIFO Control
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FDF bool // FD Frame indicator
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BRS bool // Bit Rate Switch
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DLC uint8 // Data Length Code (0-15)
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DB [64]byte // Data buffer
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}
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// FDCANRxBufferElement represents a receive buffer element
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type FDCANRxBufferElement struct {
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ESI bool // Error State Indicator
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XTD bool // Extended ID flag
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RTR bool // Remote Transmission Request
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ID uint32 // CAN identifier
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ANMF bool // Accepted Non-matching Frame
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FIDX uint8 // Filter Index
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FDF bool // FD Frame
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BRS bool // Bit Rate Switch
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DLC uint8 // Data Length Code
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RXTS uint16 // RX Timestamp
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DB [64]byte // Data buffer
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}
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// FDCANFilterConfig represents a filter configuration
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type FDCANFilterConfig struct {
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Index uint8 // Filter index (0-27 for standard, 0-7 for extended)
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Type uint8 // 0=Range, 1=Dual, 2=Classic (ID/Mask)
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Config uint8 // 0=Disable, 1=FIFO0, 2=FIFO1, 3=Reject
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ID1 uint32 // First ID or filter
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ID2 uint32 // Second ID or mask
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IsExtendedID bool // true for 29-bit ID, false for 11-bit
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}
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var (
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errFDCANInvalidTransferRate = errors.New("FDCAN: invalid TransferRate")
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errFDCANInvalidTransferRateFD = errors.New("FDCAN: invalid TransferRateFD")
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errFDCANTimeout = errors.New("FDCAN: timeout")
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errFDCANTxFifoFull = errors.New("FDCAN: Tx FIFO full")
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errFDCANRxFifoEmpty = errors.New("FDCAN: Rx FIFO empty")
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errFDCANNotStarted = errors.New("FDCAN: not started")
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)
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// DLC to bytes lookup table
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var dlcToBytes = [16]byte{0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}
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// Configure initializes the FDCAN peripheral
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func (can *FDCAN) Configure(config FDCANConfig) error {
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// Configure standby pin if specified (for CAN transceivers with standby control)
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// Setting it low enables the transceiver
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if config.Standby != NoPin {
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config.Standby.Configure(PinConfig{Mode: PinOutput})
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config.Standby.Low()
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}
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// Enable FDCAN clock
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enableFDCANClock()
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// Configure TX and RX pins
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config.Tx.ConfigureAltFunc(PinConfig{Mode: PinOutput}, can.TxAltFuncSelect)
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config.Rx.ConfigureAltFunc(PinConfig{Mode: PinInputFloating}, can.RxAltFuncSelect)
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// Exit from sleep mode
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can.Bus.SetCCCR_CSR(0)
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// Wait for sleep mode exit
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timeout := 10000
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for can.Bus.GetCCCR_CSA() != 0 {
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timeout--
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if timeout == 0 {
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return errFDCANTimeout
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}
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}
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// Request initialization
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can.Bus.SetCCCR_INIT(1)
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// Wait for init mode
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timeout = 10000
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for can.Bus.GetCCCR_INIT() == 0 {
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timeout--
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if timeout == 0 {
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return errFDCANTimeout
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}
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}
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// Enable configuration change
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can.Bus.SetCCCR_CCE(1)
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// Configure clock divider (only for FDCAN1)
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if can.Bus == stm32.FDCAN1 {
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can.Bus.SetCKDIV_PDIV(0)
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//can.Bus.CKDIV.Set(0) // No division
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}
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// Enable automatic retransmission
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can.Bus.SetCCCR_DAR(0)
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// Disable transmit pause
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can.Bus.SetCCCR_TXP(0)
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// Enable protocol exception handling
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can.Bus.SetCCCR_PXHD(0)
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// Enable FD mode with bit rate switching
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can.Bus.SetCCCR_FDOE(1)
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can.Bus.SetCCCR_BRSE(1)
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// Configure operating mode
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can.Bus.SetCCCR_TEST(0)
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can.Bus.SetCCCR_MON(0)
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can.Bus.SetCCCR_ASM(0)
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can.Bus.SetTEST_LBCK(0)
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switch config.Mode {
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case FDCANModeBusMonitoring:
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can.Bus.SetCCCR_MON(1)
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case FDCANModeInternalLoopback:
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can.Bus.SetCCCR_TEST(1)
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can.Bus.SetCCCR_MON(1)
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can.Bus.SetTEST_LBCK(1)
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case FDCANModeExternalLoopback:
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can.Bus.SetCCCR_TEST(1)
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can.Bus.SetTEST_LBCK(1)
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}
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// Set nominal bit timing
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// STM32G0 runs at 64MHz, FDCAN clock = PCLK = 64MHz
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// Bit time = (1 + NTSEG1 + NTSEG2) * tq
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// tq = (NBRP + 1) / fCAN_CLK
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if config.TransferRate == 0 {
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config.TransferRate = FDCANTransferRate500kbps
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}
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nbrp, ntseg1, ntseg2, nsjw, err := can.calculateNominalBitTiming(config.TransferRate)
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if err != nil {
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return err
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}
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can.Bus.NBTP.Set(((nsjw - 1) << 25) | ((nbrp - 1) << 16) | ((ntseg1 - 1) << 8) | (ntseg2 - 1))
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// Set data bit timing (for FD mode)
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if config.TransferRateFD == 0 {
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config.TransferRateFD = FDCANTransferRate1000kbps
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}
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if config.TransferRateFD < config.TransferRate {
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return errFDCANInvalidTransferRateFD
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}
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dbrp, dtseg1, dtseg2, dsjw, err := can.calculateDataBitTiming(config.TransferRateFD)
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if err != nil {
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return err
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}
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can.Bus.DBTP.Set(((dbrp - 1) << 16) | ((dtseg1 - 1) << 8) | ((dtseg2 - 1) << 4) | (dsjw - 1))
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// Configure message RAM
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can.configureMessageRAM()
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return nil
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}
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// Start enables the FDCAN peripheral for communication
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func (can *FDCAN) Start() error {
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// Disable configuration change
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can.Bus.SetCCCR_CCE(0)
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// Exit initialization mode
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can.Bus.SetCCCR_INIT(0)
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// Wait for normal operation
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timeout := 10000
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for can.Bus.GetCCCR_INIT() != 0 {
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timeout--
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if timeout == 0 {
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return errFDCANTimeout
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}
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}
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return nil
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}
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// Stop disables the FDCAN peripheral
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func (can *FDCAN) Stop() error {
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// Request initialization
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can.Bus.SetCCCR_INIT(1)
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// Wait for init mode
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timeout := 10000
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for can.Bus.GetCCCR_INIT() == 0 {
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timeout--
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if timeout == 0 {
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return errFDCANTimeout
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}
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}
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// Enable configuration change
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can.Bus.SetCCCR_CCE(1)
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return nil
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}
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// TxFifoIsFull returns true if the TX FIFO is full
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func (can *FDCAN) TxFifoIsFull() bool {
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return (can.Bus.TXFQS.Get() & 0x00200000) != 0 // TFQF bit
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}
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// TxFifoFreeLevel returns the number of free TX FIFO elements
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func (can *FDCAN) TxFifoFreeLevel() int {
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return int(can.Bus.TXFQS.Get() & 0x07) // TFFL[2:0]
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}
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// RxFifoSize returns the number of messages in RX FIFO 0
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func (can *FDCAN) RxFifoSize() int {
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return int(can.Bus.RXF0S.Get() & 0x0F) // F0FL[3:0]
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}
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// RxFifoIsEmpty returns true if RX FIFO 0 is empty
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func (can *FDCAN) RxFifoIsEmpty() bool {
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return (can.Bus.RXF0S.Get() & 0x0F) == 0
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}
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// TxRaw transmits a CAN frame using the raw buffer element structure
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func (can *FDCAN) TxRaw(e *FDCANTxBufferElement) error {
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// Check if TX FIFO is full
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if can.TxFifoIsFull() {
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return errFDCANTxFifoFull
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}
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// Get put index
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putIndex := (can.Bus.TXFQS.Get() >> 16) & 0x03 // TFQPI[1:0]
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// Calculate TX buffer address
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sramBase := can.getSRAMBase()
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txAddress := sramBase + sramcanTFQSA + (uintptr(putIndex) * sramcanTFQSize)
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// Build first word
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var w1 uint32
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id := e.ID
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if !e.XTD {
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// Standard ID - shift to bits [28:18]
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id = (id & 0x7FF) << 18
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}
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w1 = id & 0x1FFFFFFF
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if e.ESI {
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w1 |= fdcanElementMaskESI
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}
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if e.XTD {
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w1 |= fdcanElementMaskXTD
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}
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if e.RTR {
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w1 |= fdcanElementMaskRTR
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}
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// Build second word
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var w2 uint32
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w2 = uint32(e.DLC) << 16
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if e.FDF {
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w2 |= fdcanElementMaskFDF
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}
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if e.BRS {
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w2 |= fdcanElementMaskBRS
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}
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if e.EFC {
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w2 |= fdcanElementMaskEFC
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}
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w2 |= uint32(e.MM) << 24
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// Write to message RAM
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*(*uint32)(unsafe.Pointer(txAddress)) = w1
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*(*uint32)(unsafe.Pointer(txAddress + 4)) = w2
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|
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// Copy data bytes - must use 32-bit word access on Cortex-M0+
|
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dataLen := dlcToBytes[e.DLC&0x0F]
|
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numWords := (dataLen + 3) / 4
|
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for w := byte(0); w < numWords; w++ {
|
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var word uint32
|
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baseIdx := w * 4
|
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for b := byte(0); b < 4 && baseIdx+b < dataLen; b++ {
|
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word |= uint32(e.DB[baseIdx+b]) << (b * 8)
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}
|
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*(*uint32)(unsafe.Pointer(txAddress + 8 + uintptr(w)*4)) = word
|
||||
}
|
||||
|
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// Request transmission
|
||||
can.Bus.TXBAR.Set(1 << putIndex)
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||||
|
||||
return nil
|
||||
}
|
||||
|
||||
// Tx transmits a CAN frame with the specified ID and data
|
||||
func (can *FDCAN) Tx(id uint32, data []byte, isFD, isExtendedID bool) error {
|
||||
length := byte(len(data))
|
||||
if length > 64 {
|
||||
length = 64
|
||||
}
|
||||
if !isFD && length > 8 {
|
||||
length = 8
|
||||
}
|
||||
|
||||
e := FDCANTxBufferElement{
|
||||
ESI: false,
|
||||
XTD: isExtendedID,
|
||||
RTR: false,
|
||||
ID: id,
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||||
MM: 0,
|
||||
EFC: false,
|
||||
FDF: isFD,
|
||||
BRS: isFD,
|
||||
DLC: FDCANLengthToDlc(length, isFD),
|
||||
}
|
||||
|
||||
for i := byte(0); i < length; i++ {
|
||||
e.DB[i] = data[i]
|
||||
}
|
||||
|
||||
return can.TxRaw(&e)
|
||||
}
|
||||
|
||||
// RxRaw receives a CAN frame into the raw buffer element structure
|
||||
func (can *FDCAN) RxRaw(e *FDCANRxBufferElement) error {
|
||||
if can.RxFifoIsEmpty() {
|
||||
return errFDCANRxFifoEmpty
|
||||
}
|
||||
|
||||
// Get get index
|
||||
getIndex := (can.Bus.RXF0S.Get() >> 8) & 0x03 // F0GI[1:0]
|
||||
|
||||
// Calculate RX buffer address
|
||||
sramBase := can.getSRAMBase()
|
||||
rxAddress := sramBase + sramcanRF0SA + (uintptr(getIndex) * sramcanRF0Size)
|
||||
|
||||
// Read first word
|
||||
w1 := *(*uint32)(unsafe.Pointer(rxAddress))
|
||||
e.ESI = (w1 & fdcanElementMaskESI) != 0
|
||||
e.XTD = (w1 & fdcanElementMaskXTD) != 0
|
||||
e.RTR = (w1 & fdcanElementMaskRTR) != 0
|
||||
|
||||
if e.XTD {
|
||||
e.ID = w1 & fdcanElementMaskEXTID
|
||||
} else {
|
||||
e.ID = (w1 & fdcanElementMaskSTDID) >> 18
|
||||
}
|
||||
|
||||
// Read second word
|
||||
w2 := *(*uint32)(unsafe.Pointer(rxAddress + 4))
|
||||
e.RXTS = uint16(w2 & fdcanElementMaskTS)
|
||||
e.DLC = uint8((w2 & fdcanElementMaskDLC) >> 16)
|
||||
e.BRS = (w2 & fdcanElementMaskBRS) != 0
|
||||
e.FDF = (w2 & fdcanElementMaskFDF) != 0
|
||||
e.FIDX = uint8((w2 & fdcanElementMaskFIDX) >> 24)
|
||||
e.ANMF = (w2 & fdcanElementMaskANMF) != 0
|
||||
|
||||
// Copy data bytes - must use 32-bit word access on Cortex-M0+
|
||||
dataLen := dlcToBytes[e.DLC&0x0F]
|
||||
numWords := (dataLen + 3) / 4
|
||||
for w := byte(0); w < numWords; w++ {
|
||||
word := *(*uint32)(unsafe.Pointer(rxAddress + 8 + uintptr(w)*4))
|
||||
baseIdx := w * 4
|
||||
for b := byte(0); b < 4 && baseIdx+b < dataLen; b++ {
|
||||
e.DB[baseIdx+b] = byte(word >> (b * 8))
|
||||
}
|
||||
}
|
||||
|
||||
// Acknowledge the read
|
||||
can.Bus.RXF0A.Set(uint32(getIndex))
|
||||
|
||||
return nil
|
||||
}
|
||||
|
||||
// Rx receives a CAN frame and returns its components
|
||||
func (can *FDCAN) Rx() (id uint32, dlc byte, data []byte, isFD, isExtendedID bool, err error) {
|
||||
e := FDCANRxBufferElement{}
|
||||
err = can.RxRaw(&e)
|
||||
if err != nil {
|
||||
return 0, 0, nil, false, false, err
|
||||
}
|
||||
|
||||
length := FDCANDlcToLength(e.DLC, e.FDF)
|
||||
return e.ID, length, e.DB[:length], e.FDF, e.XTD, nil
|
||||
}
|
||||
|
||||
// SetInterrupt configures interrupt handling for the FDCAN peripheral
|
||||
func (can *FDCAN) SetInterrupt(ie uint32, callback func(*FDCAN)) error {
|
||||
if callback == nil {
|
||||
can.Bus.IE.ClearBits(ie)
|
||||
return nil
|
||||
}
|
||||
|
||||
can.Bus.IE.SetBits(ie)
|
||||
|
||||
idx := can.instance
|
||||
fdcanInstances[idx] = can
|
||||
|
||||
for i := uint(0); i < 32; i++ {
|
||||
if ie&(1<<i) != 0 {
|
||||
fdcanCallbacks[idx][i] = callback
|
||||
}
|
||||
}
|
||||
|
||||
can.Interrupt.Enable()
|
||||
return nil
|
||||
}
|
||||
|
||||
// ConfigureFilter configures a message filter
|
||||
func (can *FDCAN) ConfigureFilter(config FDCANFilterConfig) error {
|
||||
sramBase := can.getSRAMBase()
|
||||
|
||||
if config.IsExtendedID {
|
||||
// Extended filter
|
||||
if config.Index >= sramcanFLENbr {
|
||||
return errors.New("FDCAN: filter index out of range")
|
||||
}
|
||||
|
||||
filterAddr := sramBase + sramcanFLESA + (uintptr(config.Index) * sramcanFLESize)
|
||||
|
||||
// Build filter elements
|
||||
w1 := (uint32(config.Config) << 29) | (config.ID1 & 0x1FFFFFFF)
|
||||
w2 := (uint32(config.Type) << 30) | (config.ID2 & 0x1FFFFFFF)
|
||||
|
||||
*(*uint32)(unsafe.Pointer(filterAddr)) = w1
|
||||
*(*uint32)(unsafe.Pointer(filterAddr + 4)) = w2
|
||||
} else {
|
||||
// Standard filter
|
||||
if config.Index >= sramcanFLSNbr {
|
||||
return errors.New("FDCAN: filter index out of range")
|
||||
}
|
||||
|
||||
filterAddr := sramBase + sramcanFLSSA + (uintptr(config.Index) * sramcanFLSSize)
|
||||
|
||||
// Build filter element
|
||||
w := (uint32(config.Type) << 30) |
|
||||
(uint32(config.Config) << 27) |
|
||||
((config.ID1 & 0x7FF) << 16) |
|
||||
(config.ID2 & 0x7FF)
|
||||
|
||||
*(*uint32)(unsafe.Pointer(filterAddr)) = w
|
||||
}
|
||||
|
||||
return nil
|
||||
}
|
||||
|
||||
func (can *FDCAN) getSRAMBase() uintptr {
|
||||
base := uintptr(sramcanBase)
|
||||
if can.Bus == stm32.FDCAN2 {
|
||||
base += sramcanSize
|
||||
}
|
||||
return base
|
||||
}
|
||||
|
||||
func (can *FDCAN) configureMessageRAM() {
|
||||
sramBase := can.getSRAMBase()
|
||||
|
||||
// Clear message RAM
|
||||
for addr := sramBase; addr < sramBase+sramcanSize; addr += 4 {
|
||||
*(*uint32)(unsafe.Pointer(addr)) = 0
|
||||
}
|
||||
|
||||
// Configure filter counts (using RXGFC register)
|
||||
// LSS = number of standard filters, LSE = number of extended filters
|
||||
rxgfc := can.Bus.RXGFC.Get()
|
||||
rxgfc &= ^uint32(0xFF000000) // Clear LSS and LSE
|
||||
rxgfc |= (sramcanFLSNbr << 24) // Standard filters
|
||||
rxgfc |= (sramcanFLENbr << 24) & 0xFF00 // Extended filters (shifted)
|
||||
can.Bus.RXGFC.Set(rxgfc)
|
||||
}
|
||||
|
||||
func (can *FDCAN) calculateNominalBitTiming(rate FDCANTransferRate) (brp, tseg1, tseg2, sjw uint32, err error) {
|
||||
// STM32G0 FDCAN clock = 64MHz
|
||||
// Target: 80% sample point
|
||||
// Bit time = (1 + TSEG1 + TSEG2) time quanta
|
||||
switch rate {
|
||||
case FDCANTransferRate125kbps:
|
||||
// 64MHz / 32 = 2MHz, 16 tq per bit = 125kbps
|
||||
return 32, 13, 2, 4, nil
|
||||
case FDCANTransferRate250kbps:
|
||||
// 64MHz / 16 = 4MHz, 16 tq per bit = 250kbps
|
||||
return 16, 13, 2, 4, nil
|
||||
case FDCANTransferRate500kbps:
|
||||
// 64MHz / 8 = 8MHz, 16 tq per bit = 500kbps
|
||||
return 8, 13, 2, 4, nil
|
||||
case FDCANTransferRate1000kbps:
|
||||
// 64MHz / 4 = 16MHz, 16 tq per bit = 1Mbps
|
||||
return 4, 13, 2, 4, nil
|
||||
default:
|
||||
return 0, 0, 0, 0, errFDCANInvalidTransferRate
|
||||
}
|
||||
}
|
||||
|
||||
func (can *FDCAN) calculateDataBitTiming(rate FDCANTransferRate) (brp, tseg1, tseg2, sjw uint32, err error) {
|
||||
// STM32G0 FDCAN clock = 64MHz
|
||||
// For data phase, we need higher bit rates
|
||||
switch rate {
|
||||
case FDCANTransferRate125kbps:
|
||||
return 32, 13, 2, 4, nil
|
||||
case FDCANTransferRate250kbps:
|
||||
return 16, 13, 2, 4, nil
|
||||
case FDCANTransferRate500kbps:
|
||||
return 8, 13, 2, 4, nil
|
||||
case FDCANTransferRate1000kbps:
|
||||
return 4, 13, 2, 4, nil
|
||||
case FDCANTransferRate2000kbps:
|
||||
// 64MHz / 2 = 32MHz, 16 tq per bit = 2Mbps
|
||||
return 2, 13, 2, 4, nil
|
||||
case FDCANTransferRate4000kbps:
|
||||
// 64MHz / 1 = 64MHz, 16 tq per bit = 4Mbps
|
||||
return 1, 13, 2, 4, nil
|
||||
default:
|
||||
return 0, 0, 0, 0, errFDCANInvalidTransferRateFD
|
||||
}
|
||||
}
|
||||
|
||||
// FDCANDlcToLength converts a DLC value to actual byte length
|
||||
func FDCANDlcToLength(dlc byte, isFD bool) byte {
|
||||
if dlc > 15 {
|
||||
dlc = 15
|
||||
}
|
||||
length := dlcToBytes[dlc]
|
||||
if !isFD && length > 8 {
|
||||
return 8
|
||||
}
|
||||
return length
|
||||
}
|
||||
|
||||
// FDCANLengthToDlc converts a byte length to DLC value
|
||||
func FDCANLengthToDlc(length byte, isFD bool) byte {
|
||||
if !isFD {
|
||||
if length > 8 {
|
||||
return 8
|
||||
}
|
||||
return length
|
||||
}
|
||||
|
||||
switch {
|
||||
case length <= 8:
|
||||
return length
|
||||
case length <= 12:
|
||||
return 9
|
||||
case length <= 16:
|
||||
return 10
|
||||
case length <= 20:
|
||||
return 11
|
||||
case length <= 24:
|
||||
return 12
|
||||
case length <= 32:
|
||||
return 13
|
||||
case length <= 48:
|
||||
return 14
|
||||
default:
|
||||
return 15
|
||||
}
|
||||
}
|
||||
|
||||
// Interrupt handling
|
||||
var (
|
||||
fdcanInstances [2]*FDCAN
|
||||
fdcanCallbacks [2][32]func(*FDCAN)
|
||||
)
|
||||
|
||||
func fdcanHandleInterrupt(idx int) {
|
||||
if fdcanInstances[idx] == nil {
|
||||
return
|
||||
}
|
||||
|
||||
can := fdcanInstances[idx]
|
||||
ir := can.Bus.IR.Get()
|
||||
can.Bus.IR.Set(ir) // Clear interrupt flags
|
||||
|
||||
for i := uint(0); i < 32; i++ {
|
||||
if ir&(1<<i) != 0 && fdcanCallbacks[idx][i] != nil {
|
||||
fdcanCallbacks[idx][i](can)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Data returns the received data as a slice
|
||||
func (e *FDCANRxBufferElement) Data() []byte {
|
||||
return e.DB[:FDCANDlcToLength(e.DLC, e.FDF)]
|
||||
}
|
||||
|
||||
// Length returns the actual data length
|
||||
func (e *FDCANRxBufferElement) Length() byte {
|
||||
return FDCANDlcToLength(e.DLC, e.FDF)
|
||||
}
|
||||
|
||||
// enableFDCANClock enables the FDCAN peripheral clock
|
||||
func enableFDCANClock() {
|
||||
// FDCAN clock is on APB1
|
||||
stm32.RCC.SetAPBENR1_FDCANEN(1)
|
||||
}
|
||||
Reference in New Issue
Block a user