machine/esp32s3: use edge-triggered CPU interrupt for GPIO pin interrupts

When SPI is configured via the GPIO Matrix, SPI signal transitions set
GPIO.STATUS bits on the routed pins. With a level-triggered CPU interrupt
(line 8), the ISR re-enters continuously as long as any STATUS bit is
asserted — causing user GPIO callbacks to fire spuriously.

Switch cpuInterruptFromPin to CPU interrupt 10, which is edge-triggered
(level 1) on the Xtensa LX7. This ensures the ISR fires once per GPIO
event rather than looping while SPI is active.

Also move STATUS_W1TC clears to before callback dispatch so that new
GPIO events arriving during handler execution generate a fresh edge, and
add writeINTCLEAR(active) in handleInterrupt to properly acknowledge
edge-triggered CPU interrupt pending bits via the INTCLEAR register.

Fixes GPIO interrupts firing constantly when SPI and pin interrupts are
used together.

Signed-off-by: deadprogram <ron@hybridgroup.com>

src/examples/pininterrupt/xiao-esp32s3.go

@@ -6,6 +6,6 @@ import "machine"
 
 const (
 	button          = machine.D1
-	buttonMode      = machine.PinInput
+	buttonMode      = machine.PinInputPullup
 	buttonPinChange = machine.PinFalling
 )