esp32s3: add interrupt support (#5244)

* esp32s3: add interrupt support

This finally adds the long awaited support for interrupts on the
Xtensa arch. Initially just for the ESP32-S3 but then others.

Signed-off-by: deadprogram <ron@hybridgroup.com>

* esp32s3: get interrupts working correctly

There were a number of needed changes in order to get interrupts correctly working
on the esp32s3 processor:

- PS.UM=1 in interruptInit() - routed interrupts to user exception vector (0x340)
instead of kernel (0x300)
- Inline ISR in the vector slot - external handlers via j/call0 crashed (likely
clang Xtensa literal pool issue with large movi constants in separate sections)
- Disable INTENABLE (not just INT_CLR) - the USB RX interrupt is level-triggered;
clearing INT_CLR alone causes infinite re-entry since data is still in the FIFO
- Buffered() re-enables INTENABLE after draining the hardware FIFO

Signed-off-by: deadprogram <ron@hybridgroup.com>

---------

Signed-off-by: deadprogram <ron@hybridgroup.com>

targets/esp32s3.ld

@@ -39,6 +39,19 @@ SECTIONS
     *(.text.call_start_cpu0)
 } >IRAM AT >DRAM
 
+/* Xtensa exception/interrupt vector table — must be 0x400-aligned. */
+.text.exception_vectors : ALIGN(0x400)
+{
+    *(.text.exception_vectors)
+} >IRAM AT >DRAM
+
+/* Level-1 interrupt handler (called from the vector stub). */
+.text._handle_level1 : ALIGN(4)
+{
+    *(.literal._handle_level1)
+    *(.text._handle_level1)
+} >IRAM AT >DRAM
+
 /* All other code and literals */
 .text : ALIGN(4)
 {