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esp32s3: add interrupt support (#5244)
* esp32s3: add interrupt support This finally adds the long awaited support for interrupts on the Xtensa arch. Initially just for the ESP32-S3 but then others. Signed-off-by: deadprogram <ron@hybridgroup.com> * esp32s3: get interrupts working correctly There were a number of needed changes in order to get interrupts correctly working on the esp32s3 processor: - PS.UM=1 in interruptInit() - routed interrupts to user exception vector (0x340) instead of kernel (0x300) - Inline ISR in the vector slot - external handlers via j/call0 crashed (likely clang Xtensa literal pool issue with large movi constants in separate sections) - Disable INTENABLE (not just INT_CLR) - the USB RX interrupt is level-triggered; clearing INT_CLR alone causes infinite re-entry since data is still in the FIFO - Buffered() re-enables INTENABLE after draining the hardware FIFO Signed-off-by: deadprogram <ron@hybridgroup.com> --------- Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
Ron Evans
@@ -0,0 +1,223 @@
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//go:build esp32s3
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package interrupt
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import (
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"device"
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"device/esp"
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"runtime/volatile"
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"unsafe"
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)
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// State represents the previous global interrupt state.
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type State uintptr
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// Disable disables all interrupts and returns the previous interrupt state. It
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// can be used in a critical section like this:
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//
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// state := interrupt.Disable()
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// // critical section
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// interrupt.Restore(state)
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//
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// Critical sections can be nested. Make sure to call Restore in the same order
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// as you called Disable (this happens naturally with the pattern above).
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func Disable() (state State) {
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return State(device.AsmFull("rsil {}, 15", nil))
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}
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// Restore restores interrupts to what they were before. Give the previous state
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// returned by Disable as a parameter. If interrupts were disabled before
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// calling Disable, this will not re-enable interrupts, allowing for nested
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// critical sections.
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func Restore(state State) {
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device.AsmFull("wsr {state}, PS", map[string]interface{}{
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"state": state,
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})
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}
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// The ESP32-S3 (Xtensa LX7) interrupt model:
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//
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// 1. The **interrupt matrix** (INTERRUPT_CORE0) maps each peripheral source
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// (0-98) to one of 32 CPU interrupt lines via a 5-bit mapping register.
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// 2. The CPU's INTENABLE special register (SR 228) enables/disables each of
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// the 32 CPU interrupt lines independently.
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// 3. When an enabled CPU interrupt fires, the processor vectors to the
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// level-1 exception vector (offset 0x180 from VECBASE).
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// 4. The INTERRUPT special register (SR 226) shows which CPU interrupts are
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// currently pending.
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//
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// We allocate CPU interrupt lines 6..30 for use by peripherals via
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// interrupt.New(). Lines 0-5 are reserved (timer, software, etc.) and
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// line 31 is avoided because some hardware treats it specially.
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const (
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// First / last allocatable CPU interrupt for peripherals.
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firstCPUInt = 6
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lastCPUInt = 30
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)
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// cpuIntUsed tracks which CPU interrupt lines have been allocated.
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var cpuIntUsed [32]bool
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// cpuIntToPeripheral maps CPU interrupt number → peripheral IRQ source,
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// so that handleInterrupt can dispatch to the correct Go handler.
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var cpuIntToPeripheral [32]int
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// inInterrupt is set while we're inside the interrupt handler so that
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// interrupt.In() returns the correct value.
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var inInterrupt bool
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// Enable enables a CPU interrupt for the ESP32-S3. The caller must first
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// map the peripheral to a CPU interrupt line using the interrupt matrix,
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// e.g.:
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//
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// esp.INTERRUPT_CORE0.SetGPIO_INTERRUPT_PRO_MAP(cpuInt)
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// interrupt.New(cpuInt, handler).Enable()
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func (i Interrupt) Enable() error {
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if i.num < firstCPUInt || i.num > lastCPUInt {
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return errInterruptRange
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}
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// Mark as used.
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cpuIntUsed[i.num] = true
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// Read current INTENABLE, set the bit for this CPU interrupt.
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cur := readINTENABLE()
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cur |= 1 << uint(i.num)
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writeINTENABLE(cur)
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return nil
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}
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// In returns whether the CPU is currently inside an interrupt handler.
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func In() bool {
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return inInterrupt
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}
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// handleInterrupt is called from the assembly vector code in esp32s3.S.
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// It determines which CPU interrupt(s) fired and dispatches to the
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// registered Go handlers.
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//
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//export handleInterrupt
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func handleInterrupt() {
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inInterrupt = true
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// INTERRUPT register shows pending + enabled CPU interrupts.
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pending := readINTERRUPT()
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enabled := readINTENABLE()
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active := pending & enabled
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for i := firstCPUInt; i <= lastCPUInt; i++ {
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if active&(1<<uint(i)) != 0 {
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// callHandlers requires a compile-time constant, so we
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// dispatch through a switch.
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callHandler(i)
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}
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}
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inInterrupt = false
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}
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//go:inline
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func callHandler(n int) {
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switch n {
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case 6:
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callHandlers(6)
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case 7:
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callHandlers(7)
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case 8:
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callHandlers(8)
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case 9:
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callHandlers(9)
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case 10:
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callHandlers(10)
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case 11:
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callHandlers(11)
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case 12:
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callHandlers(12)
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case 13:
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callHandlers(13)
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case 14:
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callHandlers(14)
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case 15:
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callHandlers(15)
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case 16:
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callHandlers(16)
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case 17:
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callHandlers(17)
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case 18:
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callHandlers(18)
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case 19:
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callHandlers(19)
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case 20:
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callHandlers(20)
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case 21:
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callHandlers(21)
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case 22:
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callHandlers(22)
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case 23:
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callHandlers(23)
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case 24:
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callHandlers(24)
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case 25:
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callHandlers(25)
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case 26:
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callHandlers(26)
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case 27:
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callHandlers(27)
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case 28:
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callHandlers(28)
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case 29:
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callHandlers(29)
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case 30:
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callHandlers(30)
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}
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}
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// callHandlers dispatches to registered interrupt handlers for a given
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// interrupt number.
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//
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//go:linkname callHandlers runtime/interrupt.callHandlers
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func callHandlers(num int)
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var errInterruptRange = constError("interrupt for ESP32-S3 must be in range 6 through 30")
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type constError string
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func (e constError) Error() string {
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return string(e)
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}
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// readINTENABLE reads the INTENABLE special register (SR 228).
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func readINTENABLE() uint32 {
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return uint32(device.AsmFull("rsr {}, INTENABLE", nil))
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}
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// writeINTENABLE writes the INTENABLE special register (SR 228).
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func writeINTENABLE(val uint32) {
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device.AsmFull("wsr {val}, INTENABLE", map[string]interface{}{
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"val": val,
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})
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}
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// readINTERRUPT reads the INTERRUPT special register (SR 226), which
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// reflects the currently pending CPU interrupts.
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func readINTERRUPT() uint32 {
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return uint32(device.AsmFull("rsr {}, INTERRUPT", nil))
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}
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// -- Interrupt matrix helpers -----------------------------------------------
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// The ESP32-S3 interrupt matrix has one mapping register per peripheral
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// source. These are memory-mapped in the INTERRUPT_CORE0 peripheral.
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// The mapping register for peripheral source N is at:
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// base + N*4 (where base = &INTERRUPT_CORE0.PRO_MAC_INTR_MAP)
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//
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// We provide helpers to set/get the mapping for any source number.
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// mapPeripheralToInt routes peripheral IRQ source `src` to CPU interrupt
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// `cpuInt` via the interrupt matrix.
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func mapPeripheralToInt(src int, cpuInt int) {
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base := unsafe.Pointer(&esp.INTERRUPT_CORE0.PRO_MAC_INTR_MAP)
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reg := (*volatile.Register32)(unsafe.Add(base, uintptr(src)*4))
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reg.Set(uint32(cpuInt))
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}
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@@ -1,4 +1,4 @@
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//go:build xtensa
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//go:build xtensa && !esp32s3
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package interrupt
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@@ -3,8 +3,10 @@
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package runtime
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import (
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"device"
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"device/esp"
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"machine"
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"unsafe"
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)
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// This is the function called on startup after the flash (IROM/DROM) is
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@@ -75,6 +77,9 @@ func main() {
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// Initialize main system timer used for time.Now.
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initTimer()
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// Set up the Xtensa interrupt vector table.
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interruptInit()
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// Initialize the heap, call main.main, etc.
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run()
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@@ -92,6 +97,42 @@ func abort() {
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print("abort called\n")
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}
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// interruptInit installs the Xtensa vector table by writing its address
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// to the VECBASE special register and ensures all CPU interrupts are
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// initially disabled.
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func interruptInit() {
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// Disable all CPU interrupts while we configure.
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device.AsmFull("wsr {zero}, INTENABLE", map[string]interface{}{
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"zero": uintptr(0),
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})
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// Write the vector table address to VECBASE (SR 231).
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vecbase := uintptr(unsafe.Pointer(&_vector_table))
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device.AsmFull("wsr {vecbase}, VECBASE", map[string]interface{}{
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"vecbase": vecbase,
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})
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// Clear PS.EXCM and PS.INTLEVEL so that level-1 interrupts can fire.
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// The ROM bootloader leaves PS.EXCM=1 (exception mode), which masks
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// all interrupts at level ≤ EXCMLEVEL (level 1 on ESP32-S3).
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// PS.INTLEVEL may also be non-zero. Both must be 0 for peripheral
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// interrupts to trigger.
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//
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// We also set PS.UM=1 (bit 5) so that level-1 interrupts route to
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// the User exception vector at VECBASE+0x340, where our handler lives.
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// With PS.UM=0 (the ROM default), they would go to the Kernel exception
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// vector at VECBASE+0x300 which is an infinite-loop stub.
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ps := uintptr(device.AsmFull("rsr {}, PS", nil))
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ps &^= 0x1F // clear INTLEVEL (bits 0-3) and EXCM (bit 4)
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ps |= 0x20 // set PS.UM (bit 5) — use User exception vector
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device.AsmFull("wsr {ps}, PS", map[string]interface{}{
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"ps": ps,
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})
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// Synchronize pipeline after writing special registers.
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device.Asm("rsync")
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}
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//go:extern _vector_table
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var _vector_table [0]uintptr
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@@ -0,0 +1,202 @@
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// Xtensa interrupt/exception vector table for the ESP32-S3.
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//
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// The ESP32-S3 uses an Xtensa LX7 core with the windowed register ABI.
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// Interrupt vectors are placed at fixed offsets from the VECBASE special
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// register. We only handle level-1 (user) interrupts for now.
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//
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// Vector offsets (from ESP32-S3 core-isa.h XCHAL definitions):
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// 0x000 Window overflow 4
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// 0x040 Window underflow 4
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// 0x080 Window overflow 8
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// 0x0C0 Window underflow 8
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// 0x100 Window overflow 12
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// 0x140 Window underflow 12
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// 0x180 Level-2 interrupt
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// 0x1C0 Level-3 interrupt
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// 0x200 Level-4 interrupt
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// 0x240 Level-5 interrupt
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// 0x280 Debug exception (level-6)
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// 0x2C0 NMI (level-7)
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// 0x300 Kernel exception
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// 0x340 User exception (level-1 interrupt)
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// 0x3C0 Double exception
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// PS register field definitions.
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#define PS_WOE 0x00040000
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#define PS_EXCM 0x00000010
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#define PS_INTLEVEL_MASK 0x0000000F
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// -----------------------------------------------------------------------
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// Vector table — must be aligned to 0x400 (1024 bytes).
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// -----------------------------------------------------------------------
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.section .text.exception_vectors,"ax"
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.global _vector_table
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.balign 0x400
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_vector_table:
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// -----------------------------------------------------------------------
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// Offset 0x000 — Window overflow 4
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// -----------------------------------------------------------------------
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.org _vector_table + 0x000
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_window_overflow4:
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s32e a0, a5, -16
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s32e a1, a5, -12
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s32e a2, a5, -8
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s32e a3, a5, -4
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x040 — Window underflow 4
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// -----------------------------------------------------------------------
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.org _vector_table + 0x040
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_window_underflow4:
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l32e a0, a5, -16
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l32e a1, a5, -12
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l32e a2, a5, -8
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l32e a3, a5, -4
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x080 — Window overflow 8
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// -----------------------------------------------------------------------
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.org _vector_table + 0x080
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_window_overflow8:
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s32e a0, a9, -16
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l32e a0, a1, -12
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s32e a1, a9, -12
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s32e a2, a9, -8
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s32e a3, a9, -4
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s32e a4, a0, -32
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s32e a5, a0, -28
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s32e a6, a0, -24
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s32e a7, a0, -20
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x0C0 — Window underflow 8
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// -----------------------------------------------------------------------
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.org _vector_table + 0x0C0
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_window_underflow8:
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l32e a0, a9, -16
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l32e a1, a9, -12
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l32e a2, a9, -8
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l32e a7, a1, -12
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l32e a3, a9, -4
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l32e a4, a7, -32
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l32e a5, a7, -28
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l32e a6, a7, -24
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l32e a7, a7, -20
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x100 — Window overflow 12
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// -----------------------------------------------------------------------
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.org _vector_table + 0x100
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_window_overflow12:
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s32e a0, a13, -16
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l32e a0, a1, -12
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s32e a1, a13, -12
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s32e a2, a13, -8
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s32e a3, a13, -4
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s32e a4, a0, -48
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s32e a5, a0, -44
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s32e a6, a0, -40
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s32e a7, a0, -36
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s32e a8, a0, -32
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s32e a9, a0, -28
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s32e a10, a0, -24
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s32e a11, a0, -20
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x140 — Window underflow 12
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// -----------------------------------------------------------------------
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.org _vector_table + 0x140
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_window_underflow12:
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l32e a0, a13, -16
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l32e a1, a13, -12
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l32e a2, a13, -8
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l32e a11, a1, -12
|
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l32e a3, a13, -4
|
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l32e a4, a11, -48
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l32e a5, a11, -44
|
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l32e a6, a11, -40
|
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l32e a7, a11, -36
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l32e a8, a11, -32
|
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l32e a9, a11, -28
|
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l32e a10, a11, -24
|
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l32e a11, a11, -20
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rfwu
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|
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// -----------------------------------------------------------------------
|
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// Offset 0x180 — Level-2 interrupt (stub — loops forever)
|
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// -----------------------------------------------------------------------
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.org _vector_table + 0x180
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_level2_vector:
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j _level2_vector
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|
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// -----------------------------------------------------------------------
|
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// Offset 0x1C0 — Level-3 interrupt (stub — loops forever)
|
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// -----------------------------------------------------------------------
|
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.org _vector_table + 0x1C0
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_level3_vector:
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j _level3_vector
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|
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// -----------------------------------------------------------------------
|
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// Offset 0x200 — Level-4 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
|
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.org _vector_table + 0x200
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_level4_vector:
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j _level4_vector
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|
||||
// -----------------------------------------------------------------------
|
||||
// Offset 0x240 — Level-5 interrupt (stub — loops forever)
|
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// -----------------------------------------------------------------------
|
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.org _vector_table + 0x240
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_level5_vector:
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j _level5_vector
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|
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// -----------------------------------------------------------------------
|
||||
// Offset 0x280 — Debug exception / level-6 (stub — loops forever)
|
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// -----------------------------------------------------------------------
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||||
.org _vector_table + 0x280
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||||
_debug_vector:
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j _debug_vector
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|
||||
// -----------------------------------------------------------------------
|
||||
// Offset 0x2C0 — NMI / level-7 (stub — loops forever)
|
||||
// -----------------------------------------------------------------------
|
||||
.org _vector_table + 0x2C0
|
||||
_nmi_vector:
|
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j _nmi_vector
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|
||||
// -----------------------------------------------------------------------
|
||||
// Offset 0x300 — Kernel exception (stub — loops forever)
|
||||
// -----------------------------------------------------------------------
|
||||
.org _vector_table + 0x300
|
||||
_kernel_vector:
|
||||
j _kernel_vector
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
// Offset 0x340 — User exception / level-1 interrupt
|
||||
//
|
||||
// Entire handler is inline — no jump, no stack access, no memory loads.
|
||||
// Just disable all CPU interrupts via INTENABLE and return.
|
||||
// Buffered() re-enables INTENABLE after draining the hardware FIFO.
|
||||
// -----------------------------------------------------------------------
|
||||
.org _vector_table + 0x340
|
||||
.global _level1_vector
|
||||
_level1_vector:
|
||||
wsr a0, EXCSAVE1 // save a0
|
||||
movi a0, 0
|
||||
wsr a0, INTENABLE // disable ALL CPU interrupts
|
||||
rsr a0, EXCSAVE1 // restore a0
|
||||
rfe // return from exception
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
// Offset 0x3C0 — Double exception (stub — loops forever)
|
||||
// -----------------------------------------------------------------------
|
||||
.org _vector_table + 0x3C0
|
||||
_double_vector:
|
||||
j _double_vector
|
||||
@@ -12,6 +12,7 @@
|
||||
"linkerscript": "targets/esp32s3.ld",
|
||||
"extra-files": [
|
||||
"src/device/esp/esp32.S",
|
||||
"targets/esp32s3-interrupts.S",
|
||||
"src/internal/task/task_stack_esp32.S"
|
||||
],
|
||||
"binary-format": "esp32s3",
|
||||
|
||||
@@ -39,6 +39,19 @@ SECTIONS
|
||||
*(.text.call_start_cpu0)
|
||||
} >IRAM AT >DRAM
|
||||
|
||||
/* Xtensa exception/interrupt vector table — must be 0x400-aligned. */
|
||||
.text.exception_vectors : ALIGN(0x400)
|
||||
{
|
||||
*(.text.exception_vectors)
|
||||
} >IRAM AT >DRAM
|
||||
|
||||
/* Level-1 interrupt handler (called from the vector stub). */
|
||||
.text._handle_level1 : ALIGN(4)
|
||||
{
|
||||
*(.literal._handle_level1)
|
||||
*(.text._handle_level1)
|
||||
} >IRAM AT >DRAM
|
||||
|
||||
/* All other code and literals */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user