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esp32s3: add interrupt support (#5244)
* esp32s3: add interrupt support This finally adds the long awaited support for interrupts on the Xtensa arch. Initially just for the ESP32-S3 but then others. Signed-off-by: deadprogram <ron@hybridgroup.com> * esp32s3: get interrupts working correctly There were a number of needed changes in order to get interrupts correctly working on the esp32s3 processor: - PS.UM=1 in interruptInit() - routed interrupts to user exception vector (0x340) instead of kernel (0x300) - Inline ISR in the vector slot - external handlers via j/call0 crashed (likely clang Xtensa literal pool issue with large movi constants in separate sections) - Disable INTENABLE (not just INT_CLR) - the USB RX interrupt is level-triggered; clearing INT_CLR alone causes infinite re-entry since data is still in the FIFO - Buffered() re-enables INTENABLE after draining the hardware FIFO Signed-off-by: deadprogram <ron@hybridgroup.com> --------- Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
Ron Evans
@@ -0,0 +1,202 @@
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// Xtensa interrupt/exception vector table for the ESP32-S3.
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//
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// The ESP32-S3 uses an Xtensa LX7 core with the windowed register ABI.
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// Interrupt vectors are placed at fixed offsets from the VECBASE special
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// register. We only handle level-1 (user) interrupts for now.
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//
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// Vector offsets (from ESP32-S3 core-isa.h XCHAL definitions):
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// 0x000 Window overflow 4
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// 0x040 Window underflow 4
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// 0x080 Window overflow 8
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// 0x0C0 Window underflow 8
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// 0x100 Window overflow 12
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// 0x140 Window underflow 12
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// 0x180 Level-2 interrupt
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// 0x1C0 Level-3 interrupt
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// 0x200 Level-4 interrupt
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// 0x240 Level-5 interrupt
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// 0x280 Debug exception (level-6)
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// 0x2C0 NMI (level-7)
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// 0x300 Kernel exception
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// 0x340 User exception (level-1 interrupt)
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// 0x3C0 Double exception
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// PS register field definitions.
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#define PS_WOE 0x00040000
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#define PS_EXCM 0x00000010
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#define PS_INTLEVEL_MASK 0x0000000F
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// -----------------------------------------------------------------------
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// Vector table — must be aligned to 0x400 (1024 bytes).
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// -----------------------------------------------------------------------
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.section .text.exception_vectors,"ax"
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.global _vector_table
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.balign 0x400
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_vector_table:
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// -----------------------------------------------------------------------
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// Offset 0x000 — Window overflow 4
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// -----------------------------------------------------------------------
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.org _vector_table + 0x000
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_window_overflow4:
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s32e a0, a5, -16
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s32e a1, a5, -12
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s32e a2, a5, -8
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s32e a3, a5, -4
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x040 — Window underflow 4
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// -----------------------------------------------------------------------
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.org _vector_table + 0x040
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_window_underflow4:
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l32e a0, a5, -16
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l32e a1, a5, -12
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l32e a2, a5, -8
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l32e a3, a5, -4
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x080 — Window overflow 8
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// -----------------------------------------------------------------------
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.org _vector_table + 0x080
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_window_overflow8:
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s32e a0, a9, -16
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l32e a0, a1, -12
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s32e a1, a9, -12
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s32e a2, a9, -8
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s32e a3, a9, -4
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s32e a4, a0, -32
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s32e a5, a0, -28
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s32e a6, a0, -24
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s32e a7, a0, -20
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x0C0 — Window underflow 8
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// -----------------------------------------------------------------------
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.org _vector_table + 0x0C0
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_window_underflow8:
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l32e a0, a9, -16
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l32e a1, a9, -12
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l32e a2, a9, -8
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l32e a7, a1, -12
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l32e a3, a9, -4
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l32e a4, a7, -32
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l32e a5, a7, -28
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l32e a6, a7, -24
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l32e a7, a7, -20
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x100 — Window overflow 12
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// -----------------------------------------------------------------------
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.org _vector_table + 0x100
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_window_overflow12:
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s32e a0, a13, -16
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l32e a0, a1, -12
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s32e a1, a13, -12
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s32e a2, a13, -8
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s32e a3, a13, -4
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s32e a4, a0, -48
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s32e a5, a0, -44
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s32e a6, a0, -40
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s32e a7, a0, -36
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s32e a8, a0, -32
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s32e a9, a0, -28
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s32e a10, a0, -24
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s32e a11, a0, -20
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rfwo
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// -----------------------------------------------------------------------
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// Offset 0x140 — Window underflow 12
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// -----------------------------------------------------------------------
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.org _vector_table + 0x140
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_window_underflow12:
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l32e a0, a13, -16
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l32e a1, a13, -12
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l32e a2, a13, -8
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l32e a11, a1, -12
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l32e a3, a13, -4
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l32e a4, a11, -48
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l32e a5, a11, -44
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l32e a6, a11, -40
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l32e a7, a11, -36
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l32e a8, a11, -32
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l32e a9, a11, -28
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l32e a10, a11, -24
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l32e a11, a11, -20
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rfwu
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// -----------------------------------------------------------------------
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// Offset 0x180 — Level-2 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x180
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_level2_vector:
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j _level2_vector
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// -----------------------------------------------------------------------
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// Offset 0x1C0 — Level-3 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x1C0
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_level3_vector:
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j _level3_vector
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// -----------------------------------------------------------------------
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// Offset 0x200 — Level-4 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x200
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_level4_vector:
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j _level4_vector
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// -----------------------------------------------------------------------
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// Offset 0x240 — Level-5 interrupt (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x240
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_level5_vector:
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j _level5_vector
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// -----------------------------------------------------------------------
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// Offset 0x280 — Debug exception / level-6 (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x280
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_debug_vector:
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j _debug_vector
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// -----------------------------------------------------------------------
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// Offset 0x2C0 — NMI / level-7 (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x2C0
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_nmi_vector:
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j _nmi_vector
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// -----------------------------------------------------------------------
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// Offset 0x300 — Kernel exception (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x300
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_kernel_vector:
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j _kernel_vector
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// -----------------------------------------------------------------------
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// Offset 0x340 — User exception / level-1 interrupt
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//
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// Entire handler is inline — no jump, no stack access, no memory loads.
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// Just disable all CPU interrupts via INTENABLE and return.
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// Buffered() re-enables INTENABLE after draining the hardware FIFO.
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// -----------------------------------------------------------------------
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.org _vector_table + 0x340
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.global _level1_vector
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_level1_vector:
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wsr a0, EXCSAVE1 // save a0
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movi a0, 0
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wsr a0, INTENABLE // disable ALL CPU interrupts
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rsr a0, EXCSAVE1 // restore a0
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rfe // return from exception
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// -----------------------------------------------------------------------
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// Offset 0x3C0 — Double exception (stub — loops forever)
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// -----------------------------------------------------------------------
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.org _vector_table + 0x3C0
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_double_vector:
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j _double_vector
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@@ -12,6 +12,7 @@
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"linkerscript": "targets/esp32s3.ld",
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"extra-files": [
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"src/device/esp/esp32.S",
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"targets/esp32s3-interrupts.S",
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"src/internal/task/task_stack_esp32.S"
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],
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"binary-format": "esp32s3",
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@@ -39,6 +39,19 @@ SECTIONS
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*(.text.call_start_cpu0)
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} >IRAM AT >DRAM
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/* Xtensa exception/interrupt vector table — must be 0x400-aligned. */
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.text.exception_vectors : ALIGN(0x400)
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{
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*(.text.exception_vectors)
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} >IRAM AT >DRAM
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/* Level-1 interrupt handler (called from the vector stub). */
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.text._handle_level1 : ALIGN(4)
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{
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*(.literal._handle_level1)
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*(.text._handle_level1)
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} >IRAM AT >DRAM
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/* All other code and literals */
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.text : ALIGN(4)
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{
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