targets: add hifive1-qemu for testing RISC-V bare metal in QEMU

Most tests don't pass yet, so can't add this test to the standard tests, yet.
2026-09-04 19:59:03 +00:00 · 2019-11-29 22:54:27 +01:00
parent 7bdd4a1186
commit 8f9419a35d
6 changed files with 51 additions and 9 deletions
@@ -0,0 +1,13 @@
+
+/* memory map:
+ * https://github.com/sifive/freedom-e-sdk/blob/v201908-branch/bsp/sifive-hifive1/metal.default.lds
+ */
+MEMORY
+{
+    FLASH_TEXT (rw) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
+    RAM (xrw)       : ORIGIN = 0x80000000, LENGTH = 0x4000
+}
+
+_stack_size = 2K;
+
+INCLUDE "targets/riscv.ld"