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targets: add hifive1-qemu for testing RISC-V bare metal in QEMU
Most tests don't pass yet, so can't add this test to the standard tests, yet.
This commit is contained in:
committed by
Ron Evans
parent
7bdd4a1186
commit
8f9419a35d
@@ -9,7 +9,6 @@ import (
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"machine"
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"unsafe"
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"device/riscv"
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"device/sifive"
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)
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@@ -106,10 +105,3 @@ func sleepTicks(d timeUnit) {
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for ticks() < target {
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}
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}
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func abort() {
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// lock up forever
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for {
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riscv.Asm("wfi")
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}
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}
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