targets: add hifive1-qemu for testing RISC-V bare metal in QEMU

Most tests don't pass yet, so can't add this test to the standard tests,
yet.
This commit is contained in:
Ayke van Laethem
2019-11-29 22:54:27 +01:00
committed by Ron Evans
parent 7bdd4a1186
commit 8f9419a35d
6 changed files with 51 additions and 9 deletions
-8
View File
@@ -9,7 +9,6 @@ import (
"machine"
"unsafe"
"device/riscv"
"device/sifive"
)
@@ -106,10 +105,3 @@ func sleepTicks(d timeUnit) {
for ticks() < target {
}
}
func abort() {
// lock up forever
for {
riscv.Asm("wfi")
}
}