targets: add hifive1-qemu for testing RISC-V bare metal in QEMU

Most tests don't pass yet, so can't add this test to the standard tests,
yet.

src/runtime/runtime_fe310.go

@@ -9,7 +9,6 @@ import (
 	"machine"
 	"unsafe"
 
-	"device/riscv"
 	"device/sifive"
 )
 
@@ -106,10 +105,3 @@ func sleepTicks(d timeUnit) {
 	for ticks() < target {
 	}
 }
-
-func abort() {
-	// lock up forever
-	for {
-		riscv.Asm("wfi")
-	}
-}

src/runtime/runtime_fe310_baremetal.go

@@ -0,0 +1,14 @@
+// +build fe310,!qemu
+
+package runtime
+
+import (
+	"device/riscv"
+)
+
+func abort() {
+	// lock up forever
+	for {
+		riscv.Asm("wfi")
+	}
+}

src/runtime/runtime_fe310_qemu.go

@@ -0,0 +1,16 @@
+// +build fe310,qemu
+
+package runtime
+
+import (
+	"runtime/volatile"
+	"unsafe"
+)
+
+// Special memory-mapped device to exit tests, created by SiFive.
+var testExit = (*volatile.Register32)(unsafe.Pointer(uintptr(0x100000)))
+
+func abort() {
+	// Signal a successful exit.
+	testExit.Set(0x5555)
+}