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machine: sync stm32g0 with updated stm32 device files

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USART.ISR_FIFO_ENABLED => USART.ISR
          IRQ_TIM6_DAC => IRQ_TIM6_DAC_LPTIM1
            ADC.CHSELR => ADC.CHSELR0 (alternate registers 0/1)
This commit is contained in:
Michael Teichgräber
2026-02-23 16:50:34 +01:00
committed by deadprogram
parent b0ea05a853
commit 46a2a177c1
4 changed files with 5 additions and 91 deletions
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src/machine/machine_stm32_uart.go
+1 -1
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@@ -1,4 +1,4 @@
//go:build stm32 && !stm32g0
//go:build stm32
package machine