machine: sync stm32g0 with updated stm32 device files

USART.ISR_FIFO_ENABLED => USART.ISR
          IRQ_TIM6_DAC => IRQ_TIM6_DAC_LPTIM1
            ADC.CHSELR => ADC.CHSELR0 (alternate registers 0/1)
This commit is contained in:
Michael Teichgräber
2026-02-23 16:50:34 +01:00
committed by deadprogram
parent b0ea05a853
commit 46a2a177c1
4 changed files with 5 additions and 91 deletions
+1 -1
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@@ -123,7 +123,7 @@ func (a ADC) Get() uint16 {
// Select the channel to convert using CHSELR
// CHSELR uses a bitfield where bit N = 1 enables channel N
stm32.ADC.CHSELR.Set(1 << ch)
stm32.ADC.CHSELR0.Set(1 << ch)
// Wait for channel configuration ready
for stm32.ADC.GetISR_CCRDY() == 0 {
+1 -1
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@@ -1,4 +1,4 @@
//go:build stm32 && !stm32g0
//go:build stm32
package machine
+3 -3
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@@ -230,7 +230,7 @@ func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
func (uart *UART) setRegisters() {
uart.rxReg = &uart.Bus.RDR
uart.txReg = &uart.Bus.TDR
uart.statusReg = &uart.Bus.ISR_FIFO_ENABLED
uart.statusReg = &uart.Bus.ISR
uart.txEmptyFlag = stm32.USART_ISR_TXE
}
@@ -508,7 +508,7 @@ func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
case &TIM3:
return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleUPInterrupt)
case &TIM6:
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
return interrupt.New(stm32.IRQ_TIM6_DAC_LPTIM1, TIM6.handleUPInterrupt)
case &TIM7:
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
case &TIM14:
@@ -533,7 +533,7 @@ func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
case &TIM3:
return interrupt.New(stm32.IRQ_TIM3_TIM4, TIM3.handleOCInterrupt)
case &TIM6:
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
return interrupt.New(stm32.IRQ_TIM6_DAC_LPTIM1, TIM6.handleOCInterrupt)
case &TIM7:
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
case &TIM14:
-86
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@@ -1,86 +0,0 @@
//go:build stm32g0
package machine
// Peripheral abstraction layer for UARTs on the stm32g0 family.
import (
"device/stm32"
"runtime/interrupt"
"runtime/volatile"
"unsafe"
)
// UART representation
type UART struct {
Buffer *RingBuffer
Bus *stm32.USART_Type
Interrupt interrupt.Interrupt
TxAltFuncSelector uint8
RxAltFuncSelector uint8
// Registers specific to the chip
rxReg *volatile.Register32
txReg *volatile.Register32
statusReg *volatile.Register32
txEmptyFlag uint32
}
// Configure the UART.
func (uart *UART) Configure(config UARTConfig) {
// Default baud rate to 115200.
if config.BaudRate == 0 {
config.BaudRate = 115200
}
// Set the GPIO pins to defaults if they're not set
if config.TX == 0 && config.RX == 0 {
config.TX = UART_TX_PIN
config.RX = UART_RX_PIN
}
// STM32 families have different, but compatible, registers for
// basic UART functions. For each family populate the registers
// into `uart`.
uart.setRegisters()
// Enable USART clock
enableAltFuncClock(unsafe.Pointer(uart.Bus))
uart.configurePins(config)
// Set baud rate
uart.SetBaudRate(config.BaudRate)
// Enable USART port, tx, rx and rx interrupts
// STM32G0 uses CR1_FIFO_ENABLED register
uart.Bus.CR1_FIFO_ENABLED.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE)
// Enable RX IRQ
uart.Interrupt.SetPriority(0xc0)
uart.Interrupt.Enable()
}
// handleInterrupt should be called from the appropriate interrupt handler for
// this UART instance.
func (uart *UART) handleInterrupt(interrupt.Interrupt) {
uart.Receive(byte((uart.rxReg.Get() & 0xFF)))
}
// SetBaudRate sets the communication speed for the UART. Defer to chip-specific
// routines for calculation
func (uart *UART) SetBaudRate(br uint32) {
divider := uart.getBaudRateDivisor(br)
uart.Bus.BRR.Set(divider)
}
// WriteByte writes a byte of data to the UART.
func (uart *UART) writeByte(c byte) error {
uart.txReg.Set(uint32(c))
for !uart.statusReg.HasBits(uart.txEmptyFlag) {
}
return nil
}
func (uart *UART) flush() {}