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machine/attiny85: minimize SPI RAM footprint
Reduce SPI struct from ~14 bytes to 1 byte to fit in ATtiny85's limited 512 bytes of RAM. Changes: - Remove register pointers (use avr.USIDR/USISR/USICR directly) - Remove pin fields (USI pins are fixed: PB0/PB1/PB2) - Remove CS pin management (user must handle CS) - Remove frequency control (runs at max speed) - Remove LSBFirst support The SPI struct now only stores the USICR configuration byte. Co-authored-by: Ona <no-reply@ona.com>
This commit is contained in:
Jesús Espino
+51
-166
@@ -5,7 +5,6 @@ package machine
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import (
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"device/avr"
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"runtime/volatile"
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"unsafe"
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)
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const (
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@@ -384,189 +383,75 @@ type SPIConfig struct {
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Mode uint8
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}
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// SPI is the USI-based SPI implementation for ATTiny85
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// The ATTiny85 doesn't have dedicated SPI hardware, but uses the USI (Universal Serial Interface)
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// which can be configured to work as SPI in "Three-wire mode"
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// SPI is the USI-based SPI implementation for ATTiny85.
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// The ATTiny85 doesn't have dedicated SPI hardware, but uses the USI
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// (Universal Serial Interface) in three-wire mode.
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//
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// Fixed pin mapping (directly controlled by USI hardware):
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// - PB2: SCK (clock)
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// - PB1: DO/MOSI (data out)
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// - PB0: DI/MISO (data in)
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//
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// Note: CS pin must be managed by the user.
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type SPI struct {
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// USI registers
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usidr *volatile.Register8 // Data Register
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usisr *volatile.Register8 // Status Register
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usicr *volatile.Register8 // Control Register
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// The io pins for the USI-SPI
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// Note: Pin mapping is different from ISP programming pins
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sck Pin // PB2 (USCK) - Clock
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sdo Pin // PB1 (DO) - MOSI (Master Out Slave In)
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sdi Pin // PB0 (DI) - MISO (Master In Slave Out)
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cs Pin // User-defined CS pin (USI doesn't manage CS)
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// Delay cycles for frequency control (0 = max speed)
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delayCycles uint16
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// USICR value configured for the selected SPI mode
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// Single byte stores USICR configuration value
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usicrValue uint8
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// LSB-first mode (requires software bit reversal)
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lsbFirst bool
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}
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// SPI0 is the USI-based SPI interface on the ATTiny85
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var SPI0 = &SPI{
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usidr: avr.USIDR,
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usisr: avr.USISR,
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usicr: avr.USICR,
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var SPI0 = SPI{}
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sck: PB2, // USCK
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sdo: PB1, // DO (MOSI)
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sdi: PB0, // DI (MISO)
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cs: PB3, // Default CS pin (can be any available pin)
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}
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// Configure sets up the USI for SPI communication
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func (s *SPI) Configure(config SPIConfig) error {
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// Validate configuration - check that USI registers are set
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if s.usicr == (*volatile.Register8)(unsafe.Pointer(uintptr(0))) ||
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s.usisr == (*volatile.Register8)(unsafe.Pointer(uintptr(0))) ||
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s.usidr == (*volatile.Register8)(unsafe.Pointer(uintptr(0))) {
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return errSPIInvalidMachineConfig
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}
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// Configure pins
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// Configure sets up the USI for SPI communication.
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// Note: The user must configure and control the CS pin separately.
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func (spi *SPI) Configure(config SPIConfig) error {
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// Configure USI pins (directly, not via struct fields)
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// PB1 (DO/MOSI) -> OUTPUT
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// PB2 (USCK/SCK) -> OUTPUT
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// PB0 (DI/MISO) -> INPUT with pull-up
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s.sdo.Configure(PinConfig{Mode: PinOutput})
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s.sck.Configure(PinConfig{Mode: PinOutput})
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s.sdi.Configure(PinConfig{Mode: PinInput})
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// PB0 (DI/MISO) -> INPUT
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PB1.Configure(PinConfig{Mode: PinOutput})
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PB2.Configure(PinConfig{Mode: PinOutput})
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PB0.Configure(PinConfig{Mode: PinInput})
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// Enable pull-up on MISO (PB0) for better signal integrity
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avr.PORTB.SetBits(1 << uint8(s.sdi))
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// Configure CS pin - prevent glitches by setting HIGH first
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s.cs.High()
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s.cs.Configure(PinConfig{Mode: PinOutput})
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// Reset USI data register
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s.usidr.Set(0)
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s.usisr.Set(0)
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// Reset USI registers
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avr.USIDR.Set(0)
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avr.USISR.Set(0)
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// Configure USI for SPI mode:
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// - USIWM0: Three-wire mode (SPI)
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// - USICS1: External clock source (software controlled via USITC)
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// - USICLK: Clock strobe - enables counter increment on USITC toggle
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// - USICLK: Clock strobe
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// - USICS0: Controls clock phase (CPHA)
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//
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// SPI Modes:
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// Mode 0 (CPOL=0, CPHA=0): Clock idle low, sample on rising edge
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// Mode 1 (CPOL=0, CPHA=1): Clock idle low, sample on falling edge
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// Mode 2 (CPOL=1, CPHA=0): Clock idle high, sample on falling edge
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// Mode 3 (CPOL=1, CPHA=1): Clock idle high, sample on rising edge
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//
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// For USI, USICS0 controls the sampling edge when USICS1=1:
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// USICS0=0: Positive edge (rising)
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// USICS0=1: Negative edge (falling)
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switch config.Mode {
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case Mode0: // CPOL=0, CPHA=0: idle low, sample rising
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s.sck.Low()
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s.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICLK
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case Mode1: // CPOL=0, CPHA=1: idle low, sample falling
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s.sck.Low()
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s.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICS0 | avr.USICR_USICLK
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case Mode2: // CPOL=1, CPHA=0: idle high, sample falling
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s.sck.High()
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s.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICS0 | avr.USICR_USICLK
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case Mode3: // CPOL=1, CPHA=1: idle high, sample rising
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s.sck.High()
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s.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICLK
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default: // Default to Mode 0
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s.sck.Low()
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s.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICLK
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case Mode1: // CPOL=0, CPHA=1
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PB2.Low()
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spi.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICS0 | avr.USICR_USICLK
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case Mode2: // CPOL=1, CPHA=0
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PB2.High()
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spi.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICS0 | avr.USICR_USICLK
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case Mode3: // CPOL=1, CPHA=1
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PB2.High()
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spi.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICLK
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default: // Mode0: CPOL=0, CPHA=0
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PB2.Low()
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spi.usicrValue = avr.USICR_USIWM0 | avr.USICR_USICS1 | avr.USICR_USICLK
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}
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s.usicr.Set(s.usicrValue)
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// Calculate delay cycles for frequency control
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// Each bit transfer requires 2 clock toggles (rising + falling edge)
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// The loop overhead is approximately 10-15 cycles per toggle on AVR
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// We calculate additional delay cycles needed to achieve the target frequency
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if config.Frequency > 0 && config.Frequency < CPUFrequency()/2 {
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// Cycles per half-period = CPUFrequency / (2 * Frequency)
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// Subtract loop overhead (~15 cycles) to get delay cycles
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cyclesPerHalfPeriod := CPUFrequency() / (2 * config.Frequency)
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const loopOverhead = 15
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if cyclesPerHalfPeriod > loopOverhead {
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s.delayCycles = uint16(cyclesPerHalfPeriod - loopOverhead)
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} else {
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s.delayCycles = 0
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}
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} else {
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// Max speed - no delay
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s.delayCycles = 0
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}
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// Store LSBFirst setting for use in Transfer
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s.lsbFirst = config.LSBFirst
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avr.USICR.Set(spi.usicrValue)
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return nil
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}
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// reverseByte reverses the bit order of a byte (MSB <-> LSB)
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// Used for LSB-first SPI mode since USI hardware only supports MSB-first
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func reverseByte(b byte) byte {
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b = (b&0xF0)>>4 | (b&0x0F)<<4
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b = (b&0xCC)>>2 | (b&0x33)<<2
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b = (b&0xAA)>>1 | (b&0x55)<<1
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return b
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}
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// Transfer performs a single byte SPI transfer (send and receive simultaneously)
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// This implements the USI-based SPI transfer using the "clock strobing" technique
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func (s *SPI) Transfer(b byte) (byte, error) {
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// For LSB-first mode, reverse the bits before sending
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// USI hardware only supports MSB-first, so we do it in software
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if s.lsbFirst {
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b = reverseByte(b)
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}
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// Load the byte to transmit into the USI Data Register
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s.usidr.Set(b)
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// Clear the counter overflow flag by writing 1 to it (AVR quirk)
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// This also resets the 4-bit counter to 0
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s.usisr.Set(avr.USISR_USIOIF)
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// Clock the data out/in
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// We need 16 clock toggles (8 bits × 2 edges per bit)
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// The USI counter counts each clock edge, so it overflows at 16
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// After 16 toggles, the clock returns to its idle state (set by CPOL in Configure)
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//
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// IMPORTANT: Only toggle USITC here!
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// - USITC toggles the clock pin
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// - The USICR mode bits (USIWM0, USICS1, USICS0, USICLK) were set in Configure()
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// - SetBits preserves those bits and only sets USITC
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if s.delayCycles == 0 {
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// Fast path: no delay, run at maximum speed
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for !s.usisr.HasBits(avr.USISR_USIOIF) {
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s.usicr.SetBits(avr.USICR_USITC)
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}
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} else {
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// Frequency-controlled path: add delay between clock toggles
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for !s.usisr.HasBits(avr.USISR_USIOIF) {
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s.usicr.SetBits(avr.USICR_USITC)
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// Delay loop for frequency control
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// Each iteration is approximately 3 cycles on AVR (dec, brne)
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for i := s.delayCycles; i > 0; i-- {
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avr.Asm("nop")
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}
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}
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}
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// Get the received byte
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result := s.usidr.Get()
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// For LSB-first mode, reverse the received bits
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if s.lsbFirst {
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result = reverseByte(result)
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}
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return result, nil
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// Transfer performs a single byte SPI transfer (send and receive simultaneously).
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func (spi *SPI) Transfer(b byte) (byte, error) {
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// Load byte to transmit
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avr.USIDR.Set(b)
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// Clear counter overflow flag and reset counter
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avr.USISR.Set(avr.USISR_USIOIF)
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// Clock 8 bits (16 toggles)
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for !avr.USISR.HasBits(avr.USISR_USIOIF) {
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avr.USICR.SetBits(avr.USICR_USITC)
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}
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return avr.USIDR.Get(), nil
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}
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