mirror of
https://github.com/tinygo-org/drivers.git
synced 2026-07-26 10:38:41 +00:00
si5351: add many missing functions needed for convenient use.
This adds many missing functions needed for convenient use that are reinterpreted from the C code in https://github.com/dmalnati/picoinf Thank you! Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
deadprogram
+17
-4
@@ -97,11 +97,24 @@ func main() {
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// After configuring PLLs and clocks, enable the outputs.
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clockgen.EnableOutputs()
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time.Sleep(time.Second)
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clockgen.DisableOutputs()
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println("All outputs disabled for 5 seconds")
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time.Sleep(5 * time.Second)
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// Now use SetFrequency to re-set the frequencies of the outputs
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on := false
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for {
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if on {
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println("Setting Clock 0 output off")
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clockgen.OutputEnable(0, false)
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on = false
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} else {
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println("Setting Clock 0 output to 100mhz")
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clockgen.SetFrequency(100*machine.MHz, 0, si5351.PLL_A)
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on = true
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}
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time.Sleep(5 * time.Second)
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println()
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println("Clock 0: 112.5mhz")
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println("Clock 1: 13.5531mhz")
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println("Clock 2: 10.706khz")
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}
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}
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@@ -62,3 +62,18 @@ const (
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MULTISYNTH_DIV_6 = 6
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MULTISYNTH_DIV_8 = 8
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)
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// Frequency constants (in Hz)
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const (
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CLKOUT_MIN_FREQ = 8000 // 8 kHz
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CLKOUT_MAX_FREQ = 150000000 // 150 MHz
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MULTISYNTH_MAX_FREQ = 150000000 // 150 MHz
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MULTISYNTH_SHARE_MAX = 100000000 // 100 MHz
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MULTISYNTH_DIVBY4_FREQ = 150000000 // 150 MHz
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PLL_VCO_MIN = 600000000 // 600 MHz
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PLL_VCO_MAX = 900000000 // 900 MHz
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)
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const (
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SI5351_PLL_C_MAX = 1048575
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)
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+310
-129
@@ -134,6 +134,23 @@ func (d *Device) DisableOutputs() error {
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return d.rw.Write8(OUTPUT_ENABLE_CONTROL, 0xFF)
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}
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// packRegSet packs P1, P2, P3 values into the 8-byte register format
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// used by both PLL and Multisynth configuration.
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// For multisynth, rDivBits should contain the R divider value shifted left by 4.
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// For PLL, rDivBits should be 0.
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func packRegSet(p1, p2, p3 uint32, rDivBits uint8) [8]byte {
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var data [8]byte
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data[0] = uint8((p3 & 0xFF00) >> 8)
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data[1] = uint8(p3 & 0xFF)
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data[2] = uint8((p1&0x30000)>>16) | rDivBits
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data[3] = uint8((p1 & 0xFF00) >> 8)
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data[4] = uint8(p1 & 0xFF)
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data[5] = uint8(((p3 & 0xF0000) >> 12) | ((p2 & 0xF0000) >> 16))
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data[6] = uint8((p2 & 0xFF00) >> 8)
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data[7] = uint8(p2 & 0xFF)
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return data
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}
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// ConfigurePLL sets the multiplier for the specified PLL
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// pll The PLL to configure, which must be one of the following:
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// - PLL_A
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@@ -163,42 +180,24 @@ func (d *Device) DisableOutputs() error {
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// See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
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func (d *Device) ConfigurePLL(pll uint8, mult uint8, num uint32, denom uint32) error {
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// Basic validation
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if !d.initialised {
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switch {
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case !d.initialised:
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return ErrNotInitialised
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}
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// mult = 15..90
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if !((mult > 14) && (mult < 91)) {
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case !((mult > 14) && (mult < 91)):
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return ErrInvalidParameter
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}
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// Avoid divide by zero
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if !(denom > 0) {
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case !(denom > 0):
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return ErrInvalidParameter
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}
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// 20-bit limit
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if !(num <= 0xFFFFF) {
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case !(num <= 0xFFFFF):
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return ErrInvalidParameter
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}
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// 20-bit limit
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if !(denom <= 0xFFFFF) {
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case !(denom <= 0xFFFFF):
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return ErrInvalidParameter
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}
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// PLL Multiplier Equations
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//
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// P1 register is an 18-bit value using following formula:
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//
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// P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512
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//
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// P2 register is a 20-bit value using the following formula:
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//
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// P2[19:0] = 128 * num - denom * floor(128*(num/denom))
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//
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// P3 register is a 20-bit value using the following formula:
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//
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// P3[19:0] = denom
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//
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// Set PLL config registers
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// Calculate PLL register values
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var p1, p2, p3 uint32
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if num == 0 {
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// Integer mode
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@@ -218,16 +217,8 @@ func (d *Device) ConfigurePLL(pll uint8, mult uint8, num uint32, denom uint32) e
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baseaddr = 34
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}
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// The datasheet is a nightmare of typos and inconsistencies here!
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data := [8]byte{}
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data[0] = uint8((p3 & 0x0000FF00) >> 8)
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data[1] = uint8(p3 & 0x000000FF)
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data[2] = uint8((p1 & 0x00030000) >> 16)
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data[3] = uint8((p1 & 0x0000FF00) >> 8)
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data[4] = uint8(p1 & 0x000000FF)
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data[5] = uint8(((p3 & 0x000F0000) >> 12) | ((p2 & 0x000F0000) >> 16))
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data[6] = uint8((p2 & 0x0000FF00) >> 8)
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data[7] = uint8(p2 & 0x000000FF)
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// Pack and write registers
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data := packRegSet(p1, p2, p3, 0)
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if err := d.bus.Tx(uint16(baseaddr), data[:], nil); err != nil {
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return err
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}
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@@ -305,120 +296,58 @@ func (d *Device) ConfigurePLL(pll uint8, mult uint8, num uint32, denom uint32) e
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// used, but this isn't currently implemented in the driver.
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func (d *Device) ConfigureMultisynth(output uint8, pll uint8, div uint32, num uint32, denom uint32) error {
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// Basic validation
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if !d.initialised {
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switch {
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case !d.initialised:
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return ErrNotInitialised
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}
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// Channel range
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if !(output < 3) {
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case !(output < 3):
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return fmt.Errorf("output channel must be between 0 and 2")
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}
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// Divider integer value
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if !((div > 3) && (div < 2049)) {
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case !((div > 3) && (div < 2049)):
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return ErrInvalidParameter
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}
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// Avoid divide by zero
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if !(denom > 0) {
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case !(denom > 0):
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return ErrInvalidParameter
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}
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// 20-bit limit
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if !(num <= 0xFFFFF) {
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case !(num <= 0xFFFFF):
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return ErrInvalidParameter
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}
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// 20-bit limit
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if !(denom <= 0xFFFFF) {
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case !(denom <= 0xFFFFF):
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return ErrInvalidParameter
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// Make sure the requested PLL has been initialised
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case pll == PLL_A && !d.pllaConfigured:
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return ErrInvalidParameter
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case pll == PLL_B && !d.pllbConfigured:
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return ErrInvalidParameter
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}
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// Make sure the requested PLL has been initialised
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if pll == PLL_A && !d.pllaConfigured {
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return ErrInvalidParameter
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}
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if pll == PLL_B && !d.pllbConfigured {
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return ErrInvalidParameter
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}
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// Output Multisynth Divider Equations
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//
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// where: a = div, b = num and c = denom
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//
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// P1 register is an 18-bit value using following formula:
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//
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// P1[17:0] = 128 * a + floor(128*(b/c)) - 512
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//
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// P2 register is a 20-bit value using the following formula:
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//
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// P2[19:0] = 128 * b - c * floor(128*(b/c))
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//
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// P3 register is a 20-bit value using the following formula:
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//
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// P3[19:0] = c
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//
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// Set PLL config registers
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var p1, p2, p3 uint32
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if num == 0 {
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// Calculate register values
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var reg si5351RegSet
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switch {
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case num == 0:
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// Integer mode
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p1 = 128*div - 512
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p2 = 0
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p3 = denom
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} else if denom == 1 {
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reg.p1 = 128*div - 512
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reg.p2 = 0
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reg.p3 = denom
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case denom == 1:
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// Fractional mode, simplified calculations
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p1 = 128*div + 128*num - 512
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p2 = 128*num - 128
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p3 = 1
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} else {
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reg.p1 = 128*div + 128*num - 512
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reg.p2 = 128*num - 128
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reg.p3 = 1
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default:
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// Fractional mode
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p1 = uint32(128*float64(div) + math.Floor(128*(float64(num)/float64(denom))) - 512)
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p2 = uint32(128*float64(num) - float64(denom)*math.Floor(128*(float64(num)/float64(denom))))
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p3 = denom
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reg.p1 = uint32(128*float64(div) + math.Floor(128*(float64(num)/float64(denom))) - 512)
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reg.p2 = uint32(128*float64(num) - float64(denom)*math.Floor(128*(float64(num)/float64(denom))))
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reg.p3 = denom
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}
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// Get the appropriate starting point for the PLL registers
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baseaddr := uint8(0)
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switch output {
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case 0:
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baseaddr = MULTISYNTH0_PARAMETERS_1
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case 1:
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baseaddr = MULTISYNTH1_PARAMETERS_1
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case 2:
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baseaddr = MULTISYNTH2_PARAMETERS_1
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}
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// Determine if we should use integer mode
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intMode := num == 0
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// Set the MSx config registers
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data := [8]byte{}
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data[0] = uint8((p3 & 0xFF00) >> 8)
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data[1] = uint8(p3 & 0xFF)
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data[2] = uint8(((p1 & 0x30000) >> 16)) | d.lastRdivValue[output]
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data[3] = uint8((p1 & 0xFF00) >> 8)
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data[4] = uint8(p1 & 0xFF)
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data[5] = uint8(((p3 & 0xF0000) >> 12) | ((p2 & 0xF0000) >> 16))
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data[6] = uint8((p2 & 0xFF00) >> 8)
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data[7] = uint8(p2 & 0xFF)
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if err := d.bus.Tx(uint16(baseaddr), data[:], nil); err != nil {
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return err
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}
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// Use existing R divider value (0 if not previously set)
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rDiv := d.lastRdivValue[output] >> 4
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// Configure the clk control and enable the output
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// TODO: Check if the clk control byte needs to be updated.
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clkControlReg := uint8(0x0F) // 8mA drive strength, MS0 as CLK0 source, Clock not inverted, powered up
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if pll == PLL_B {
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clkControlReg |= (1 << 5) // Uses PLLB
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}
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if num == 0 {
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clkControlReg |= (1 << 6) // Integer mode
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}
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var register uint8
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switch output {
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case 0:
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register = CLK0_CONTROL
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case 1:
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register = CLK1_CONTROL
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case 2:
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register = CLK2_CONTROL
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}
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return d.rw.Write8(register, clkControlReg)
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return d.setMS(output, reg, intMode, rDiv, pll)
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}
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func (d *Device) ConfigureRdiv(output uint8, div uint8) error {
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@@ -446,3 +375,255 @@ func (d *Device) ConfigureRdiv(output uint8, div uint8) error {
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data = (data & 0x0F) | d.lastRdivValue[output]
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return d.rw.Write8(register, data)
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}
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// si5351RegSet holds the register values for multisynth configuration
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type si5351RegSet struct {
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p1 uint32
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p2 uint32
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p3 uint32
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}
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var ErrFrequencyOutOfRange = errors.New("Si5351 frequency out of range")
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var ErrClockConflict = errors.New("Si5351 clock conflict with existing configuration")
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// SetFrequency sets the clock frequency of the specified CLK output.
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// Frequency range is 8 kHz to 150 MHz.
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//
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// freq - Output frequency in Hz
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// output - Clock output (0, 1, or 2 for this driver)
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// pll - The PLL to use (PLL_A or PLL_B)
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func (d *Device) SetFrequency(freq uint64, output uint8, pll uint8) error {
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switch {
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case !d.initialised:
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return ErrNotInitialised
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case output > 2:
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return ErrInvalidParameter
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}
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switch {
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// Lower bounds check
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case freq < CLKOUT_MIN_FREQ:
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freq = CLKOUT_MIN_FREQ
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// Upper bounds check
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case freq > MULTISYNTH_MAX_FREQ:
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freq = MULTISYNTH_MAX_FREQ
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}
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// Select the proper R divider value for low frequencies
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rDiv := d.selectRDiv(&freq)
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// Calculate PLL and multisynth parameters
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var pllFreq uint64
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switch {
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case pll == PLL_A && d.pllaConfigured:
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pllFreq = uint64(d.pllaFreq)
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case pll == PLL_B && d.pllbConfigured:
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pllFreq = uint64(d.pllbFreq)
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default:
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// PLL not configured, calculate optimal PLL frequency
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pllFreq = d.calculatePLLFreq(freq)
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}
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// Calculate multisynth divider parameters
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msReg := d.multisynthCalc(freq, pllFreq)
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// Determine if we should use integer mode
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intMode := msReg.p2 == 0
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// Configure PLL if not already configured or if we need a new frequency
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if (pll == PLL_A && !d.pllaConfigured) || (pll == PLL_B && !d.pllbConfigured) {
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if err := d.setPLL(pllFreq, pll); err != nil {
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return err
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}
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}
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// Set multisynth registers
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if err := d.setMS(output, msReg, intMode, rDiv, pll); err != nil {
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return err
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}
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// Enable output
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return d.OutputEnable(output, true)
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}
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// selectRDiv selects the appropriate R divider for low frequencies
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// and modifies the frequency accordingly
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func (d *Device) selectRDiv(freq *uint64) uint8 {
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var rDiv uint8 = 0
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if *freq >= CLKOUT_MIN_FREQ && *freq < CLKOUT_MIN_FREQ*2 {
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rDiv = R_DIV_128
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*freq *= 128
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} else if *freq >= CLKOUT_MIN_FREQ*2 && *freq < CLKOUT_MIN_FREQ*4 {
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rDiv = R_DIV_64
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*freq *= 64
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} else if *freq >= CLKOUT_MIN_FREQ*4 && *freq < CLKOUT_MIN_FREQ*8 {
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rDiv = R_DIV_32
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*freq *= 32
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} else if *freq >= CLKOUT_MIN_FREQ*8 && *freq < CLKOUT_MIN_FREQ*16 {
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rDiv = R_DIV_16
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*freq *= 16
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} else if *freq >= CLKOUT_MIN_FREQ*16 && *freq < CLKOUT_MIN_FREQ*32 {
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rDiv = R_DIV_8
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*freq *= 8
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} else if *freq >= CLKOUT_MIN_FREQ*32 && *freq < CLKOUT_MIN_FREQ*64 {
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rDiv = R_DIV_4
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*freq *= 4
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} else if *freq >= CLKOUT_MIN_FREQ*64 && *freq < CLKOUT_MIN_FREQ*128 {
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rDiv = R_DIV_2
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*freq *= 2
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}
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return rDiv
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}
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// calculatePLLFreq calculates an optimal PLL frequency for the given output frequency
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func (d *Device) calculatePLLFreq(freq uint64) uint64 {
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// Try to find an integer divider that puts PLL in valid range (600-900 MHz)
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// Start with a divider that gives us a PLL freq near 750 MHz (middle of range)
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targetPLL := uint64(750000000)
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divider := targetPLL / freq
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// Ensure divider is in valid range (8-900 for fractional, 4/6/8 for integer)
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switch {
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case divider < 8:
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divider = 8
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case divider > 900:
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divider = 900
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}
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pllFreq := freq * divider
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// Ensure PLL frequency is in valid range
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switch {
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case pllFreq < PLL_VCO_MIN:
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pllFreq = PLL_VCO_MIN
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case pllFreq > PLL_VCO_MAX:
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pllFreq = PLL_VCO_MAX
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}
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return pllFreq
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}
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// multisynthCalc calculates the multisynth register values
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func (d *Device) multisynthCalc(freq, pllFreq uint64) si5351RegSet {
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var reg si5351RegSet
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// Calculate the division ratio
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// divider = pllFreq / freq
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a := uint32(pllFreq / freq)
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remainder := pllFreq % freq
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// Calculate b and c for fractional part
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// We use c = SI5351_PLL_C_MAX (max 20-bit value) for best resolution
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c := uint32(SI5351_PLL_C_MAX)
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b := uint32((uint64(remainder) * uint64(c)) / freq)
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// Calculate P1, P2, P3
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// P1 = 128 * a + floor(128 * b / c) - 512
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// P2 = 128 * b - c * floor(128 * b / c)
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// P3 = c
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floor128bc := uint32((128 * uint64(b)) / uint64(c))
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||||
reg.p1 = 128*a + floor128bc - 512
|
||||
reg.p2 = 128*b - c*floor128bc
|
||||
reg.p3 = c
|
||||
|
||||
return reg
|
||||
}
|
||||
|
||||
// setPLL configures the PLL with the specified frequency
|
||||
func (d *Device) setPLL(pllFreq uint64, pll uint8) error {
|
||||
// Calculate PLL multiplier from crystal frequency
|
||||
// pllFreq = crystalFreq * (a + b/c)
|
||||
xtalFreq := uint64(d.crystalFreq)
|
||||
|
||||
a := uint32(pllFreq / xtalFreq)
|
||||
remainder := pllFreq % xtalFreq
|
||||
|
||||
// Use max denominator for best resolution
|
||||
c := uint32(SI5351_PLL_C_MAX)
|
||||
b := uint32((remainder * uint64(c)) / xtalFreq)
|
||||
|
||||
return d.ConfigurePLL(pll, uint8(a), b, c)
|
||||
}
|
||||
|
||||
// setMS sets the multisynth registers for the specified output
|
||||
func (d *Device) setMS(output uint8, reg si5351RegSet, intMode bool, rDiv uint8, pll uint8) error {
|
||||
// Get the appropriate starting point for the registers
|
||||
var baseaddr uint8
|
||||
switch output {
|
||||
case 0:
|
||||
baseaddr = MULTISYNTH0_PARAMETERS_1
|
||||
case 1:
|
||||
baseaddr = MULTISYNTH1_PARAMETERS_1
|
||||
case 2:
|
||||
baseaddr = MULTISYNTH2_PARAMETERS_1
|
||||
default:
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
|
||||
// Store R divider value
|
||||
d.lastRdivValue[output] = (rDiv & 0x07) << 4
|
||||
|
||||
// Pack and write registers
|
||||
data := packRegSet(reg.p1, reg.p2, reg.p3, d.lastRdivValue[output])
|
||||
if err := d.bus.Tx(uint16(baseaddr), data[:], nil); err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
// Configure the clk control register
|
||||
clkControlReg := uint8(0x0F) // 8mA drive strength, powered up
|
||||
if pll == PLL_B {
|
||||
clkControlReg |= (1 << 5) // Use PLLB
|
||||
}
|
||||
if intMode {
|
||||
clkControlReg |= (1 << 6) // Integer mode
|
||||
}
|
||||
|
||||
var clkReg uint8
|
||||
switch output {
|
||||
case 0:
|
||||
clkReg = CLK0_CONTROL
|
||||
case 1:
|
||||
clkReg = CLK1_CONTROL
|
||||
case 2:
|
||||
clkReg = CLK2_CONTROL
|
||||
}
|
||||
|
||||
return d.rw.Write8(clkReg, clkControlReg)
|
||||
}
|
||||
|
||||
// GetFreqStep returns the frequency step size of the radio in Hz.
|
||||
// This is the smallest frequency increment that can be achieved,
|
||||
// determined by the PLL frequency and denominator resolution.
|
||||
// If pll is PLL_A, uses PLLA settings; if PLL_B, uses PLLB settings.
|
||||
// Returns 0 if the specified PLL is not configured.
|
||||
func (d *Device) GetFreqStep(pll uint8) uint64 {
|
||||
// The frequency step at the output is:
|
||||
// step = pllFreq / (SI5351_PLL_C_MAX * multisynth_divider)
|
||||
//
|
||||
// However, since multisynth divider varies per output, we return
|
||||
// the base step from the PLL, which is:
|
||||
// step = pllFreq / SI5351_PLL_C_MAX
|
||||
|
||||
var pllFreq uint64
|
||||
|
||||
switch pll {
|
||||
case PLL_A:
|
||||
if !d.pllaConfigured {
|
||||
return 0
|
||||
}
|
||||
pllFreq = uint64(d.pllaFreq)
|
||||
case PLL_B:
|
||||
if !d.pllbConfigured {
|
||||
return 0
|
||||
}
|
||||
pllFreq = uint64(d.pllbFreq)
|
||||
default:
|
||||
return 0
|
||||
}
|
||||
|
||||
return pllFreq / SI5351_PLL_C_MAX
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user