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si5351: add support for si5351 (#810)
* si5351: add support for si5351 Adds support for the si5351 I2C programmable clock generator using code from @chiefMarlin which used code from @conotto which somehow never got merged. Thank you everyone! Signed-off-by: deadprogram <ron@hybridgroup.com> * refactor: use regmap instead of legacy package to avoid heap allocations Signed-off-by: deadprogram <ron@hybridgroup.com> --------- Signed-off-by: deadprogram <ron@hybridgroup.com>
This commit is contained in:
Ron Evans
GitHub
@@ -0,0 +1,107 @@
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package main
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import (
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"machine"
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"time"
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"tinygo.org/x/drivers/si5351"
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)
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// Simple demo of the SI5351 clock generator.
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// This is like the Arduino library example:
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// https://github.com/adafruit/Adafruit_Si5351_Library/blob/master/examples/si5351/si5351.ino
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// Which will configure the chip with:
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// - PLL A at 900mhz
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// - PLL B at 616.66667mhz
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// - Clock 0 at 112.5mhz, using PLL A as a source divided by 8
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// - Clock 1 at 13.5531mhz, using PLL B as a source divided by 45.5
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// - Clock 2 at 10.76khz, using PLL B as a source divided by 900 and further divided with an R divider of 64.
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func main() {
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time.Sleep(5 * time.Second)
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println("Si5351 Clockgen Test")
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println()
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// Configure I2C bus
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machine.I2C0.Configure(machine.I2CConfig{})
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// Create driver instance
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clockgen := si5351.New(machine.I2C0)
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// Verify device wired properly
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connected, err := clockgen.Connected()
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if err != nil {
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println("Unable to read device status")
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time.Sleep(time.Second)
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}
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if !connected {
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for {
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println("Unable to detect si5351 device")
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time.Sleep(time.Second)
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}
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}
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// Initialise device
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clockgen.Configure()
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// Now configue the PLLs and clock outputs.
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// The PLLs can be configured with a multiplier and division of the on-board
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// 25mhz reference crystal. For example configure PLL A to 900mhz by multiplying
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// by 36. This uses an integer multiplier which is more accurate over time
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// but allows less of a range of frequencies compared to a fractional
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// multiplier shown next.
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clockgen.ConfigurePLL(si5351.PLL_A, 36, 0, 1) // Multiply 25mhz by 36
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println("PLL A frequency: 900mhz")
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// And next configure PLL B to 616.6667mhz by multiplying 25mhz by 24.667 using
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// the fractional multiplier configuration. Notice you specify the integer
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// multiplier and then a numerator and denominator as separate values, i.e.
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// numerator 2 and denominator 3 means 2/3 or 0.667. This fractional
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// configuration is susceptible to some jitter over time but can set a larger
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// range of frequencies.
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clockgen.ConfigurePLL(si5351.PLL_B, 24, 2, 3) // Multiply 25mhz by 24.667 (24 2/3)
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println("PLL B frequency: 616.6667mhz")
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// Now configure the clock outputs. Each is driven by a PLL frequency as input
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// and then further divides that down to a specific frequency.
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// Configure clock 0 output to be driven by PLL A divided by 8, so an output
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// of 112.5mhz (900mhz / 8). Again this uses the most precise integer division
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// but can't set as wide a range of values.
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clockgen.ConfigureMultisynth(0, si5351.PLL_A, 8, 0, 1) // Divide by 8 (8 0/1)
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println("Clock 0: 112.5mhz")
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// Next configure clock 1 to be driven by PLL B divided by 45.5 to get
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// 13.5531mhz (616.6667mhz / 45.5). This uses fractional division and again
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// notice the numerator and denominator are explicitly specified. This is less
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// precise but allows a large range of frequencies.
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clockgen.ConfigureMultisynth(1, si5351.PLL_B, 45, 1, 2) // Divide by 45.5 (45 1/2)
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println("Clock 1: 13.5531mhz")
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// Finally configure clock 2 to be driven by PLL B divided once by 900 to get
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// down to 685.15 khz and then further divided by a special R divider that
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// divides 685.15 khz by 64 to get a final output of 10.706khz.
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clockgen.ConfigureMultisynth(2, si5351.PLL_B, 900, 0, 1) // Divide by 900 (900 0/1)
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// Set the R divider, this can be a value of:
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// - R_DIV_1: divider of 1
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// - R_DIV_2: divider of 2
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// - R_DIV_4: divider of 4
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// - R_DIV_8: divider of 8
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// - R_DIV_16: divider of 16
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// - R_DIV_32: divider of 32
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// - R_DIV_64: divider of 64
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// - R_DIV_128: divider of 128
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clockgen.ConfigureRdiv(2, si5351.R_DIV_64)
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println("Clock 2: 10.706khz")
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// After configuring PLLs and clocks, enable the outputs.
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clockgen.EnableOutputs()
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for {
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time.Sleep(5 * time.Second)
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println()
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println("Clock 0: 112.5mhz")
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println("Clock 1: 13.5531mhz")
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println("Clock 2: 10.706khz")
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}
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}
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@@ -0,0 +1,64 @@
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package si5351
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// The I2C address which this device listens to.
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const AddressDefault = 0x60 // Assumes ADDR pin is low
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const AddressAlternative = 0x61 // Assumes ADDR pin is high
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const (
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OUTPUT_ENABLE_CONTROL = 3
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CLK0_CONTROL = 16
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CLK1_CONTROL = 17
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CLK2_CONTROL = 18
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CLK3_CONTROL = 19
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CLK4_CONTROL = 20
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CLK5_CONTROL = 21
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CLK6_CONTROL = 22
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CLK7_CONTROL = 23
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MULTISYNTH0_PARAMETERS_1 = 42
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MULTISYNTH0_PARAMETERS_3 = 44
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MULTISYNTH1_PARAMETERS_1 = 50
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MULTISYNTH1_PARAMETERS_3 = 52
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MULTISYNTH2_PARAMETERS_1 = 58
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MULTISYNTH2_PARAMETERS_3 = 60
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SPREAD_SPECTRUM_PARAMETERS = 149
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PLL_RESET = 177
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CRYSTAL_INTERNAL_LOAD_CAPACITANCE = 183
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)
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const (
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CRYSTAL_LOAD_6PF = (1 << 6)
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CRYSTAL_LOAD_8PF = (2 << 6)
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CRYSTAL_LOAD_10PF = (3 << 6)
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)
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const (
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CRYSTAL_FREQ_25MHZ = 25000000
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CRYSTAL_FREQ_27MHZ = 27000000
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)
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const (
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PLL_A = iota
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PLL_B
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)
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const (
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R_DIV_1 = iota
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R_DIV_2
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R_DIV_4
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R_DIV_8
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R_DIV_16
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R_DIV_32
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R_DIV_64
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R_DIV_128
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)
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const (
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MULTISYNTH_DIV_4 = 4
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MULTISYNTH_DIV_6 = 6
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MULTISYNTH_DIV_8 = 8
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)
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@@ -0,0 +1,448 @@
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package si5351
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import (
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"encoding/binary"
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"errors"
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"fmt"
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"math"
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"tinygo.org/x/drivers"
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"tinygo.org/x/drivers/internal/regmap"
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)
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// Device wraps an I2C connection to a SI5351 device.
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type Device struct {
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bus drivers.I2C
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Address uint8
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rw regmap.Device8I2C
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initialised bool
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crystalFreq uint32
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crystalLoad uint8
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pllaConfigured bool
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pllaFreq uint32
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pllbConfigured bool
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pllbFreq uint32
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lastRdivValue [3]uint8
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}
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var ErrNotInitialised = errors.New("Si5351 not initialised")
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var ErrInvalidParameter = errors.New("Si5351 invalid parameter")
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// New creates a new SI5351 connection. The I2C bus must already be configured.
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//
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// This function only creates the Device object, it does not touch the device.
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func New(bus drivers.I2C) Device {
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rw := regmap.Device8I2C{}
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rw.SetBus(bus, AddressDefault, binary.BigEndian)
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return Device{
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bus: bus,
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rw: rw,
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Address: AddressDefault,
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crystalFreq: CRYSTAL_FREQ_25MHZ,
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crystalLoad: CRYSTAL_LOAD_10PF,
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}
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}
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// Configure sets up the device for communication
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// TODO error handling
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func (d *Device) Configure() error {
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// // Disable all outputs setting CLKx_DIS high
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d.rw.Write8(OUTPUT_ENABLE_CONTROL, 0xFF)
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// Set the load capacitance for the XTAL
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d.rw.Write8(CRYSTAL_INTERNAL_LOAD_CAPACITANCE, d.crystalLoad)
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// Power down all output drivers
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buf := []byte{CLK0_CONTROL, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}
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d.bus.Tx(uint16(d.Address), buf, nil)
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// Disable spread spectrum output.
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if err := d.DisableSpreadSpectrum(); err != nil {
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return err
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}
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d.initialised = true
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return nil
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}
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// Connected returns whether a device at SI5351 address has been found.
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func (d *Device) Connected() (bool, error) {
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if err := d.bus.Tx(uint16(d.Address), []byte{}, []byte{0}); err != nil {
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return false, err
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}
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return true, nil
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}
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// EnableSpreadSpectrum enables spread spectrum modulation to reduce EMI.
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func (d *Device) EnableSpreadSpectrum() error {
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data, err := d.rw.Read8(SPREAD_SPECTRUM_PARAMETERS)
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if err != nil {
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return err
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}
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data |= 0x80
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return d.rw.Write8(SPREAD_SPECTRUM_PARAMETERS, data)
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}
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func (d *Device) DisableSpreadSpectrum() error {
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data, err := d.rw.Read8(SPREAD_SPECTRUM_PARAMETERS)
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if err != nil {
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return err
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}
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data &^= 0x80
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return d.rw.Write8(SPREAD_SPECTRUM_PARAMETERS, data)
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}
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func (d *Device) OutputEnable(output uint8, enable bool) error {
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if !d.initialised {
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return ErrNotInitialised
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}
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// Read the current value of the OUTPUT_ENABLE_CONTROL register
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regVal, err := d.rw.Read8(OUTPUT_ENABLE_CONTROL)
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if err != nil {
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return err
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}
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// Modify regVal based on clk and enable
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if enable {
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regVal &= ^(1 << output)
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} else {
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regVal |= (1 << output)
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}
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// Write the modified value back to the OUTPUT_ENABLE_CONTROL register
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return d.rw.Write8(OUTPUT_ENABLE_CONTROL, regVal)
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}
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func (d *Device) EnableOutputs() error {
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if !d.initialised {
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return ErrNotInitialised
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}
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return d.rw.Write8(OUTPUT_ENABLE_CONTROL, 0x00)
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}
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func (d *Device) DisableOutputs() error {
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if !d.initialised {
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return ErrNotInitialised
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}
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return d.rw.Write8(OUTPUT_ENABLE_CONTROL, 0xFF)
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}
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// ConfigurePLL sets the multiplier for the specified PLL
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// pll The PLL to configure, which must be one of the following:
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// - PLL_A
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// - PLL_B
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//
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// mult The PLL integer multiplier (must be between 15 and 90)
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//
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// num The 20-bit numerator for fractional output (0..1,048,575).
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// Set this to '0' for integer output.
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//
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// denom The 20-bit denominator for fractional output (1..1,048,575).
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// Set this to '1' or higher to avoid divider by zero errors.
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//
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// PLL Configuration
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// fVCO is the PLL output, and must be between 600..900MHz, where:
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//
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// fVCO = fXTAL * (a+(b/c))
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//
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// fXTAL = the crystal input frequency
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// a = an integer between 15 and 90
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// b = the fractional numerator (0..1,048,575)
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// c = the fractional denominator (1..1,048,575)
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//
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// NOTE: Try to use integers whenever possible to avoid clock jitter
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// (only use the a part, setting b to '0' and c to '1').
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//
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// See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
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func (d *Device) ConfigurePLL(pll uint8, mult uint8, num uint32, denom uint32) error {
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// Basic validation
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if !d.initialised {
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return ErrNotInitialised
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}
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// mult = 15..90
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if !((mult > 14) && (mult < 91)) {
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return ErrInvalidParameter
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}
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// Avoid divide by zero
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if !(denom > 0) {
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return ErrInvalidParameter
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}
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// 20-bit limit
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if !(num <= 0xFFFFF) {
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return ErrInvalidParameter
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}
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// 20-bit limit
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if !(denom <= 0xFFFFF) {
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return ErrInvalidParameter
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}
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// PLL Multiplier Equations
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//
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// P1 register is an 18-bit value using following formula:
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//
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// P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512
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//
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// P2 register is a 20-bit value using the following formula:
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//
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// P2[19:0] = 128 * num - denom * floor(128*(num/denom))
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//
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// P3 register is a 20-bit value using the following formula:
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//
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// P3[19:0] = denom
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//
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// Set PLL config registers
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var p1, p2, p3 uint32
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if num == 0 {
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// Integer mode
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p1 = 128*uint32(mult) - 512
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p2 = num
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p3 = denom
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} else {
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// Fractional mode
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p1 = uint32(128*float64(mult) + math.Floor(128*(float64(num)/float64(denom))) - 512)
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p2 = uint32(128*float64(num) - float64(denom)*math.Floor(128*(float64(num)/float64(denom))))
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p3 = denom
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}
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// Get the appropriate starting point for the PLL registers
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baseaddr := uint8(26)
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if pll == PLL_B {
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baseaddr = 34
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}
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// The datasheet is a nightmare of typos and inconsistencies here!
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data := [8]byte{}
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data[0] = uint8((p3 & 0x0000FF00) >> 8)
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data[1] = uint8(p3 & 0x000000FF)
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data[2] = uint8((p1 & 0x00030000) >> 16)
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data[3] = uint8((p1 & 0x0000FF00) >> 8)
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data[4] = uint8(p1 & 0x000000FF)
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data[5] = uint8(((p3 & 0x000F0000) >> 12) | ((p2 & 0x000F0000) >> 16))
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data[6] = uint8((p2 & 0x0000FF00) >> 8)
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data[7] = uint8(p2 & 0x000000FF)
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if err := d.bus.Tx(uint16(baseaddr), data[:], nil); err != nil {
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return err
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}
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// Reset both PLLs
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if err := d.rw.Write8(PLL_RESET, (1<<7)|(1<<5)); err != nil {
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return err
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}
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// Store the frequency settings for use with the Multisynth helper
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fvco := float64(d.crystalFreq) * (float64(mult) + (float64(num) / float64(denom)))
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if pll == PLL_A {
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d.pllaConfigured = true
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d.pllaFreq = uint32(math.Floor(fvco))
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} else {
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d.pllbConfigured = true
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d.pllbFreq = uint32(math.Floor(fvco))
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}
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return nil
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}
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// ConfigureMultisynth divider, which determines the
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// output clock frequency based on the specified PLL input.
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//
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// output The output channel to use (0..2)
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//
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// pll The PLL input source to use, which must be one of:
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// - PLL_A
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// - PLL_B
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//
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// div The integer divider for the Multisynth output.
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//
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// If pure integer values are used, this value must be one of:
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// - MULTISYNTH_DIV_4
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// - MULTISYNTH_DIV_6
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// - MULTISYNTH_DIV_8
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// If fractional output is used, this value must be between 8 and 900.
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//
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// num The 20-bit numerator for fractional output (0..1,048,575).
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//
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// Set this to '0' for integer output.
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//
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// denom The 20-bit denominator for fractional output (1..1,048,575).
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//
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// Set this to '1' or higher to avoid divide by zero errors.
|
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//
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// # Output Clock Configuration
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//
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// The multisynth dividers are applied to the specified PLL output,
|
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// and are used to reduce the PLL output to a valid range (500kHz
|
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// to 160MHz). The relationship can be seen in this formula, where
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// fVCO is the PLL output frequency and MSx is the multisynth divider:
|
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//
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// fOUT = fVCO / MSx
|
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//
|
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// Valid multisynth dividers are 4, 6, or 8 when using integers,
|
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// or any fractional values between 8 + 1/1,048,575 and 900 + 0/1
|
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// The following formula is used for the fractional mode divider:
|
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//
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// a + b / c
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//
|
||||
// a = The integer value, which must be 4, 6 or 8 in integer mode (MSx_INT=1) or 8..900 in fractional mode (MSx_INT=0).
|
||||
// b = The fractional numerator (0..1,048,575)
|
||||
// c = The fractional denominator (1..1,048,575)
|
||||
//
|
||||
// NOTE: Try to use integers whenever possible to avoid clock jitter
|
||||
// NOTE: For output frequencies > 150MHz, you must set the divider
|
||||
//
|
||||
// to 4 and adjust to PLL to generate the frequency (for example
|
||||
// a PLL of 640 to generate a 160MHz output clock). This is not
|
||||
// yet supported in the driver, which limits frequencies to 500kHz .. 150MHz.
|
||||
//
|
||||
// NOTE: For frequencies below 500kHz (down to 8kHz) Rx_DIV must be
|
||||
//
|
||||
// used, but this isn't currently implemented in the driver.
|
||||
func (d *Device) ConfigureMultisynth(output uint8, pll uint8, div uint32, num uint32, denom uint32) error {
|
||||
// Basic validation
|
||||
if !d.initialised {
|
||||
return ErrNotInitialised
|
||||
}
|
||||
// Channel range
|
||||
if !(output < 3) {
|
||||
return fmt.Errorf("output channel must be between 0 and 2")
|
||||
}
|
||||
// Divider integer value
|
||||
if !((div > 3) && (div < 2049)) {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
// Avoid divide by zero
|
||||
if !(denom > 0) {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
// 20-bit limit
|
||||
if !(num <= 0xFFFFF) {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
// 20-bit limit
|
||||
if !(denom <= 0xFFFFF) {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
|
||||
// Make sure the requested PLL has been initialised
|
||||
if pll == PLL_A && !d.pllaConfigured {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
if pll == PLL_B && !d.pllbConfigured {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
|
||||
// Output Multisynth Divider Equations
|
||||
//
|
||||
// where: a = div, b = num and c = denom
|
||||
//
|
||||
// P1 register is an 18-bit value using following formula:
|
||||
//
|
||||
// P1[17:0] = 128 * a + floor(128*(b/c)) - 512
|
||||
//
|
||||
// P2 register is a 20-bit value using the following formula:
|
||||
//
|
||||
// P2[19:0] = 128 * b - c * floor(128*(b/c))
|
||||
//
|
||||
// P3 register is a 20-bit value using the following formula:
|
||||
//
|
||||
// P3[19:0] = c
|
||||
//
|
||||
|
||||
// Set PLL config registers
|
||||
var p1, p2, p3 uint32
|
||||
if num == 0 {
|
||||
// Integer mode
|
||||
p1 = 128*div - 512
|
||||
p2 = 0
|
||||
p3 = denom
|
||||
} else if denom == 1 {
|
||||
// Fractional mode, simplified calculations
|
||||
p1 = 128*div + 128*num - 512
|
||||
p2 = 128*num - 128
|
||||
p3 = 1
|
||||
} else {
|
||||
// Fractional mode
|
||||
p1 = uint32(128*float64(div) + math.Floor(128*(float64(num)/float64(denom))) - 512)
|
||||
p2 = uint32(128*float64(num) - float64(denom)*math.Floor(128*(float64(num)/float64(denom))))
|
||||
p3 = denom
|
||||
}
|
||||
|
||||
// Get the appropriate starting point for the PLL registers
|
||||
baseaddr := uint8(0)
|
||||
switch output {
|
||||
case 0:
|
||||
baseaddr = MULTISYNTH0_PARAMETERS_1
|
||||
case 1:
|
||||
baseaddr = MULTISYNTH1_PARAMETERS_1
|
||||
case 2:
|
||||
baseaddr = MULTISYNTH2_PARAMETERS_1
|
||||
}
|
||||
|
||||
// Set the MSx config registers
|
||||
data := [8]byte{}
|
||||
data[0] = uint8((p3 & 0xFF00) >> 8)
|
||||
data[1] = uint8(p3 & 0xFF)
|
||||
data[2] = uint8(((p1 & 0x30000) >> 16)) | d.lastRdivValue[output]
|
||||
data[3] = uint8((p1 & 0xFF00) >> 8)
|
||||
data[4] = uint8(p1 & 0xFF)
|
||||
data[5] = uint8(((p3 & 0xF0000) >> 12) | ((p2 & 0xF0000) >> 16))
|
||||
data[6] = uint8((p2 & 0xFF00) >> 8)
|
||||
data[7] = uint8(p2 & 0xFF)
|
||||
if err := d.bus.Tx(uint16(baseaddr), data[:], nil); err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
// Configure the clk control and enable the output
|
||||
// TODO: Check if the clk control byte needs to be updated.
|
||||
clkControlReg := uint8(0x0F) // 8mA drive strength, MS0 as CLK0 source, Clock not inverted, powered up
|
||||
if pll == PLL_B {
|
||||
clkControlReg |= (1 << 5) // Uses PLLB
|
||||
}
|
||||
if num == 0 {
|
||||
clkControlReg |= (1 << 6) // Integer mode
|
||||
}
|
||||
|
||||
var register uint8
|
||||
switch output {
|
||||
case 0:
|
||||
register = CLK0_CONTROL
|
||||
case 1:
|
||||
register = CLK1_CONTROL
|
||||
case 2:
|
||||
register = CLK2_CONTROL
|
||||
}
|
||||
|
||||
return d.rw.Write8(register, clkControlReg)
|
||||
}
|
||||
|
||||
func (d *Device) ConfigureRdiv(output uint8, div uint8) error {
|
||||
// Channel range
|
||||
if !(output < 3) {
|
||||
return ErrInvalidParameter
|
||||
}
|
||||
|
||||
var register uint8
|
||||
switch output {
|
||||
case 0:
|
||||
register = MULTISYNTH0_PARAMETERS_3
|
||||
case 1:
|
||||
register = MULTISYNTH1_PARAMETERS_3
|
||||
case 2:
|
||||
register = MULTISYNTH2_PARAMETERS_3
|
||||
}
|
||||
|
||||
data, err := d.rw.Read8(register)
|
||||
if err != nil {
|
||||
return err
|
||||
}
|
||||
|
||||
d.lastRdivValue[output] = (div & 0x07) << 4
|
||||
data = (data & 0x0F) | d.lastRdivValue[output]
|
||||
return d.rw.Write8(register, data)
|
||||
}
|
||||
@@ -144,6 +144,7 @@ tinygo build -size short -o ./build/test.hex -target=pico ./examples/tmc5160/mai
|
||||
tinygo build -size short -o ./build/test.uf2 -target=nicenano ./examples/sharpmem/main.go
|
||||
tinygo build -size short -o ./build/test.hex -target=feather-nrf52840 ./examples/max6675/main.go
|
||||
tinygo build -size short -o ./build/test.hex -target=pico ./examples/ens160/main.go
|
||||
tinygo build -size short -o ./build/test.hex -target=pico ./examples/si5351/main.go
|
||||
# network examples (espat)
|
||||
tinygo build -size short -o ./build/test.hex -target=challenger-rp2040 ./examples/net/ntpclient/
|
||||
# network examples (wifinina)
|
||||
|
||||
Reference in New Issue
Block a user