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add MDIOBitBang
This commit is contained in:
Patricio Whittingslow
@@ -0,0 +1,187 @@
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package phy
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import (
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"errors"
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)
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var _ MDIOBus = (*MDIOBitBang)(nil) // compile time guarantee of interface implementation.
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const (
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mdioRead = 0b10
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mdioWrite = 0b01
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miaddrc45 = 1 << 30
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c45bit = 1 << 15
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c45Addr = c45bit | 0b00
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c45Read = c45bit | 0b11
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c45Write = c45bit | 0b01
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)
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// MDIOBitBang provides a software defined(bitbang) MDIO/MDC management interface for PHY register access
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// as the STA (Management station, this implementation) which communicates to the PHY (Physical layer device).
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// Inspired by linux/v3.13.1/source/drivers/net/phy/mdio-bitbang.c
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// Below is a TinyGo oriented HAL needed to use MDIOBitBang. MDC is clock line, MDIO is data line.
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//
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// const mdioDelay = 340 * time.Nanosecond // MDIO spec max turnaround time
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// pinMDIO.Configure(machine.PinConfig{Mode: machine.PinInputPullup})
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// pinMDC.Configure(machine.PinConfig{Mode: machine.PinOutput})
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// pinMDC.Low()
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// var mdio2 phy.MDIOBitBang
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// mdio2.Configure(func(outBit bool) {
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// // sendBit: set data, clock high, clock low
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// if outBit {
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// pinMDIO.Configure(machine.PinConfig{Mode: machine.PinInputPullup})
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// } else {
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// pinMDIO.Low()
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// pinMDIO.Configure(machine.PinConfig{Mode: machine.PinOutput})
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// }
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// time.Sleep(mdioDelay)
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// pinMDC.High()
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// time.Sleep(mdioDelay)
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// pinMDC.Low()
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// }, func() (inBit bool) {
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// // getBit: clock high, read, clock low
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// time.Sleep(mdioDelay)
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// pinMDC.High()
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// time.Sleep(mdioDelay)
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// pinMDC.Low()
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// return pinMDIO.Get()
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// }, func(setOut bool) {
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// // setDir: configure pin direction
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// if setOut {
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// pinMDIO.Configure(machine.PinConfig{Mode: machine.PinInputPullup})
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// } else {
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// pinMDIO.Configure(machine.PinConfig{Mode: machine.PinInput})
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// }
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// })
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type MDIOBitBang struct {
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_sendBit func(bit bool)
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_getBit func() (inputBit bool)
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_setDir func(output bool)
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}
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// Configure initializes the MDIO bit-bang interface with the given pin control callbacks.
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func (m *MDIOBitBang) Configure(sendBit func(bit bool), getBit func() bool, setDir func(setOut bool)) {
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if sendBit == nil || getBit == nil || setDir == nil {
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panic("nil callback")
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}
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m._getBit = getBit
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m._sendBit = sendBit
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m._setDir = setDir
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m.reset()
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}
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func (m *MDIOBitBang) reset() {
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// setting direction to output releases the bus.
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m.setDir(true)
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}
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// Read reads a PHY register. Uses Clause 45 framing if devAddr is non-zero.
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func (m *MDIOBitBang) Read(phyAddr, devAddr uint8, regAddr uint16) (uint16, error) {
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isC45 := devAddr != 0
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if isC45 {
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m.cmdAddr2(phyAddr, devAddr, regAddr)
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m.cmd(c45Read, phyAddr, devAddr)
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} else {
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m.cmd(mdioRead, phyAddr, uint8(regAddr))
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}
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m.setDir(false)
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// Check turnaround bit, PHY should drive it to zero.
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if m.getBit() {
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// PHY did not drive low, as would be expected.
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// Ensure flush:
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for range 32 {
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m.getBit()
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}
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return 0xffff, errors.New("PHY did not drive turnaround low")
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}
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ret := m.getNum(16)
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m.getBit()
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return ret, nil
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}
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// Write writes a value to a PHY register. Uses Clause 45 framing if devAddr is non-zero.
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func (m *MDIOBitBang) Write(phyAddr, devAddr uint8, regAddr, value uint16) error {
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isC45 := devAddr != 0
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if isC45 {
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m.cmdAddr2(phyAddr, devAddr, regAddr)
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m.cmd(c45Write, phyAddr, devAddr)
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} else {
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m.cmd(mdioWrite, phyAddr, uint8(regAddr))
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}
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// send turnaround (10)
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m.sendBit(true)
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m.sendBit(false)
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m.sendNum(value, 16)
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m.setDir(false)
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m.getBit()
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return nil
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}
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func (m *MDIOBitBang) cmdAddr2(phy, dev uint8, reg uint16) {
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m.cmd(c45Addr, phy, dev)
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// turnaround 10.
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m.sendBit(true)
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m.sendBit(false)
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m.sendNum(reg, 16)
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m.setDir(false)
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m.getBit()
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}
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func (m *MDIOBitBang) cmd(op uint16, phy uint8, reg uint8) {
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const writeDir = true
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m.setDir(writeDir)
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// Preamble, 32 bits of 1.
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for range 32 {
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m.sendBit(true)
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}
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// Start of frame: 01
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// Clause 45 op uses 00=start, 11=read, 10=write
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m.sendBit(false)
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m.sendBit(op&c45bit == 0)
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m.sendBit((op>>1)&1 != 0)
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m.sendBit((op>>0)&1 != 0)
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m.sendNum(uint16(phy), 5)
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m.sendNum(uint16(reg), 5)
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}
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func (m *MDIOBitBang) sendNum(val uint16, bits int) {
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for i := bits - 1; i >= 0; i-- {
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m.sendBit((val>>i)&1 != 0)
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}
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}
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func (m *MDIOBitBang) getNum(bits int) (ret uint16) {
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for i := bits - 1; i >= 0; i-- {
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ret <<= 1
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ret |= uint16(b2u8(m.getBit()))
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}
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return ret
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}
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// MDIO low-level clock operations
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// Reference: https://github.com/sandeepmistry/pico-rmii-ethernet/blob/main/examples/httpd/main.c
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// Reference: netif_rmii_ethernet_mdio_clock_out() and netif_rmii_ethernet_mdio_clock_in()
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// from rmii_ethernet.c
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// setDir configures pins preparing for write/read operations.
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func (m *MDIOBitBang) setDir(outWrite bool) {
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m._setDir(outWrite)
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}
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func (m *MDIOBitBang) sendBit(b bool) {
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m._sendBit(b)
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}
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func (m *MDIOBitBang) getBit() bool {
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return m._getBit()
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}
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func b2u8(b bool) uint8 {
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if b {
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return 1
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}
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return 0
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}
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+30
@@ -40,6 +40,36 @@ All RMII signals are synchronous to a continuous 50 MHz reference clock. Two mod
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## Tx0/Tx1/TxEN and CLKREF/RETCLK interface
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### Frame Transmission Sequence
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First 8 bytes in transmission are preamble and start of frame delimiter (SFD).
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The preamble is composed of 7 bytes, all dibits valued 0b01, so TX0=1, TX1=0.
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The SFD is composed of 3 0b01 dibits and a 0b11 dibit where both TX0 and TX1 are high for a single CLKREF cycle. After the final SFD(0b11) dibit the frame data is presented of the wire.
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TX_EN is asserted synchronously with the first dibit of preamble and remains HIGH throughout the entire frame (preamble, SFD, payload, CRC).
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Example at 100M link mode:
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```
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REF_CLK: _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_ ...
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TX_EN: __|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾ ... (HIGH until end of frame)
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TX0: __|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾...‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|.D ...
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TX1: _______________________________...____________|‾‾‾|.A ...
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TXD[1:0]: 00|01 |01 |01 |01 |01 |01 |01 |...|01 |01 |01 |11 |DA|TA|...
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└───────────── Preamble (28 dibits) ─────────┘└SFD┘└─ Frame data ─...
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```
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**Inter-Packet Gap (IPG)**: After TX_EN deasserts, TXD[1:0] must be held at 00 for a minimum of 96 bit times (48 dibits = 12 bytes at 100M). This is the minimum gap required between consecutive frame transmissions.
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```
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End of frame with IPG at 100M link mode:
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REF_CLK: _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_ ...
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TX_EN: ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____________________________ ...
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TXD[1:0]: ...data...|CR|C |00|00|00|00|00|00|00|00|...
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└CRC┘ └──── IPG (≥48 dibits) ────...
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```
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### Practical Tx example:
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To illustrate programatically we'll suppose we have a hardware which requires a byte for every clock. Each byte contains 3 bits to be sent out: Tx0,Tx1,TxEn bits.
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This is not a contrived example, it is how Sandeep Mistry's and Rob Scott's LAN8720 drivers work.
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