Add praline gpio (#3218)

* Implement antenna bias control for Praline and update GPIO configurations
* Add GPIO power management functions and update board initialization for Praline
* Refactor power management functions for Praline and update GPIO configurations
* Update GPIO configurations for Praline and enable power control pins. AA_EN enabled
* Refactor GPIO configuration for Praline: update array size definitions and clean up comments
* Add P1 and P2 control functions for PRALINE
* Introduced P1_Function and P2_Function enums in ClockManager to manage multiplexer control.
* mplemented set_p1_control and set_p2_control methods for configuring P1 and P2 control pins based on specified functions.
* Updated clock_manager.hpp and clock_manager.cpp to include new functionality.
* Modified MAX2837 and MAX2839 initialization to conditionally configure GPIO based on PRALINE.
* Adjusted RFFC507x and RFFC507x_SPI initialization to include GPIO setup for PRALINE.
- Refactored RF path initialization to remove unnecessary GPIO setup.
- Updated board configuration for PRALINE to reflect new GPIO settings and pin configurations.
- Cleaned up FPGA bridge code by removing unused pin configuration functions.
- Adjusted SCU array size in pal_lld.h for PRALINE.
- Enhanced hackrf_gpio.hpp to define multiplexer control pins for PRALINE.
- Modified LED setup to accommodate active-low configuration for PRALINE.

* Refactor GPIO and power control functions

- Removed unused power control function declarations from board.h.
- Enhanced gpio.hpp with new pin setup functions and GPIO control structures for PRALINE.
- Consolidated multiplexer control pin definitions into gpio_control namespace.
- Moved power control function implementations to gpio.cpp, including detailed VAA power management logic.
- Updated power control functions to handle both PRALINE and HackRF R9 configurations.
- Cleaned up hackrf_gpio.hpp by removing redundant multiplexer control definitions.

* Refactor GPIO control for PRALINE: update MAX2831 and RFFC507x configurations, add new GPIO mappings

* Refactor GPIO configurations for PRALINE: update anti-aliasing filter pin mapping, enhance LED setup logic, and add placeholder GPIO entries.

* Refactor GPIO configurations for PRALINE: update LED mappings and remove unused anti-aliasing filter GPIO entry.

firmware/application/clock_manager.cpp

@@ -31,6 +31,11 @@ using namespace hackrf::one;
 #include "lpc43xx_cpp.hpp"
 using namespace lpc43xx;
 
+#ifdef PRALINE
+#include "hackrf_gpio.hpp"
+#include "gpio.hpp"
+#endif
+
 #ifdef PRALINE
 extern "C" {
 #include "fpga_bridge.h"
@@ -429,32 +434,10 @@ static void portapack_tcxo_disable() {
 using namespace hackrf::one;
 
 void ClockManager::init_clock_generator() {
-#ifdef PRALINE
-    /* Route the PRALINE P22 10MHz reference to the Si5351 CLKIN pin. */
-    LPC_SCU->SFSP[2][10] = 0xF0;
-    LPC_SCU->SFSP[6][8] = 0xF4;
-    LPC_SCU->SFSP[6][9] = 0xF0;
-    LPC_SCU->SFSP[1][20] = 0xF0;
-
-    gpio_p1_ctrl0.output();
-    gpio_p1_ctrl1.output();
-    gpio_p1_ctrl2.output();
-    gpio_clkin_ctrl.output();
-
-    gpio_p1_ctrl0.write(0);
-    gpio_p1_ctrl1.write(0);
-    gpio_p1_ctrl2.write(1);
-    gpio_clkin_ctrl.write(1);
-
-    chThdSleepMilliseconds(20);
-
-#else
-    // HackRF One r9: GPIO0_8 (mcu_clk_en) gates Si5351 CLK2/CLK7 to GP_CLKIN
     if (hackrf_r9) {
         gpio_r9_mcu_clk_en.output();
         gpio_r9_mcu_clk_en.write(1);
     }
-#endif
 
     clock_generator.reset();
     clock_generator.set_crystal_internal_load_capacitance(CrystalInternalLoadCapacitance::XTAL_CL_8pF);
@@ -1224,3 +1207,74 @@ void ClockManager::enable_clock_output(bool enable) {
     }
 #endif
 }
+
+#ifdef PRALINE
+
+void ClockManager::set_p1_control(P1_Function func) {
+    // Truth table based on P1_Control.csv (L=clear, H=set)
+    switch (func) {
+        case P1_Function::TriggerIn:
+            gpio_control::p1_ctrl2.clear();
+            gpio_control::p1_ctrl1.clear();
+            gpio_control::p1_ctrl0.clear();
+            break;
+        case P1_Function::AuxClk1:
+            gpio_control::p1_ctrl2.clear();
+            gpio_control::p1_ctrl1.clear();
+            gpio_control::p1_ctrl0.set();
+            break;
+        case P1_Function::ClkIn:
+            gpio_control::p1_ctrl2.clear();
+            gpio_control::p1_ctrl1.set();
+            gpio_control::p1_ctrl0.clear();
+            break;
+        case P1_Function::TriggerOut:
+            gpio_control::p1_ctrl2.clear();
+            gpio_control::p1_ctrl1.set();
+            gpio_control::p1_ctrl0.set();
+            break;
+        case P1_Function::P22_ClkIn:
+            gpio_control::p1_ctrl2.set();
+            gpio_control::p1_ctrl1.clear();
+            gpio_control::p1_ctrl0.clear();
+            break;
+        case P1_Function::P2_5:
+            gpio_control::p1_ctrl2.set();
+            gpio_control::p1_ctrl1.clear();
+            gpio_control::p1_ctrl0.set();
+            break;
+        case P1_Function::NotConnected:
+            gpio_control::p1_ctrl2.set();
+            gpio_control::p1_ctrl1.set();
+            gpio_control::p1_ctrl0.clear();
+            break;
+        case P1_Function::AuxClk2:
+            gpio_control::p1_ctrl2.set();
+            gpio_control::p1_ctrl1.set();
+            gpio_control::p1_ctrl0.set();
+            break;
+    }
+}
+
+void ClockManager::set_p2_control(P2_Function func) {
+    // Ensure all P2 control pins are configured as outputs
+
+    // Truth table based on P2_Control.csv (L=clear, H=set)
+    switch (func) {
+        case P2_Function::Clk3:
+            // CTRL0 is 'X' (don't care) according to CSV, we default it to Low (clear)
+            gpio_control::p2_ctrl1.clear();
+            gpio_control::p2_ctrl0.clear();
+            break;
+        case P2_Function::TriggerIn:
+            gpio_control::p2_ctrl1.set();
+            gpio_control::p2_ctrl0.clear();
+            break;
+        case P2_Function::TriggerOut:
+            gpio_control::p2_ctrl1.set();
+            gpio_control::p2_ctrl0.set();
+            break;
+    }
+}
+
+#endif