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Imrpoved sound quality in analog_audio_app, and added Nyquist protection option to BBW filter for praline. (#3054)
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stafur
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@@ -247,21 +247,20 @@ constexpr ClockControls si5351c_clock_control_common{{
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constexpr ClockControls si5351a_clock_control_common{{
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#ifdef PRALINE
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// CLK0: MAX5864 (ADC)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK1: SCT_CLK - iCE40 FPGA timing clock
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK2: LPC43xx MCU
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK3: CLKOUT (optional) SMA Port P1
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK4: PRALINE MAX2831 reference (40 MHz) - INVERTED per hackrf_usb, 4mA, Integer mode
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK5: PRALINE RFFC5072 reference (40 MHz) - INVERTED, 6mA, Integer mode
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// This matches HackRF One OG configuration for RFFC5072
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK6: SMA Port P2
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK0: MAX5864 (ADC) - 4mA, Inverted (Standard for Praline sync)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_On},
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// CLK1: SCT_CLK (iCE40 FPGA) - 6mA, Inverted (Fixes 30-60Hz Drumming)
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK2: LPC43xx MCU - 4mA, Normal (Must be Integer for MCU stability)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK3: CLKOUT SMA Port P1 - 8mA, Normal
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK4: MAX2831 reference (40 MHz) - Inverted (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK5: RFFC5072 reference (40 MHz) - Inverted (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK6: SMA Port P2 - 8mA, Normal
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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#else
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off},
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@@ -274,7 +273,6 @@ constexpr ClockControls si5351a_clock_control_common{{
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// CLK6: Not used
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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#endif
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// CLK7: Not used
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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@@ -469,7 +467,9 @@ void ClockManager::init_clock_generator() {
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si5351a_clock_control_common[6].ms_src(ref_pll),
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si5351a_clock_control_common[7].ms_src(ref_pll),
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}};
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clock_generator.set_clock_control(si5351_clock_control);
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// clock_generator.set_clock_control(si5351_clock_control);
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// Use single-byte writes instead of multi-byte
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clock_generator.set_clock_control_single_byte(si5351_clock_control);
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#else
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if (hackrf_r9) {
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const PLLReg pll_reg = (reference.source == ReferenceSource::Xtal)
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@@ -686,53 +686,41 @@ void ClockManager::disable_if_clocks() {
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void ClockManager::set_sampling_frequency(const uint32_t frequency) {
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#ifdef PRALINE
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/* PRALINE: CLK0=AFE_CLK runs at sample rate (VCO/divider/2)
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* CLK1=SCT_CLK runs at 2x sample rate (VCO/divider/1)
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* Reference: hackrf_core.c sample_rate_frac_set() lines 580-582
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*/
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/* PRALINE: Match HackRF USB sample_rate_frac_set()
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* Reference: hackrf_usb radio.c lines 29-91, hackrf_core.c lines 501-685 */
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_base_band_frequency = frequency; // Store frequency for StatusViews
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/*
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* PRALINE sample rate strategy from GSG hackrf_usb radio.c:
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*
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* 1. Run ADC at the highest rate possible (up to 40 MHz)
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* PRALINE sample rate strategy:
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* 1. Maximize AFE rate to push Nyquist above MAX2831's 11.6 MHz LPF minimum
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* 2. Use FPGA decimation to achieve desired output rate
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* 3. This makes the analog LPF effective at rejecting aliases
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* 4. Re-apply frequency after to reconfigure LPF bandwidth
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* 3. Ensure AFE rate is achievable by Si5351 (clean division from 800 MHz VCO)
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*/
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// 20 MHz, since GSG reference of 40MHz caused shifts at certain values.
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constexpr uint32_t MAX_AFE_RATE = 20000000;
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constexpr uint8_t MAX_N = 5; // Max decimation = 2^5 = 32
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constexpr uint32_t MAX_AFE_RATE = 40000000; // Use 40 MHz per GSG reference
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constexpr uint8_t MAX_N = 5;
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// Calculate optimal decimation factor for RX
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// Start with n=1 (minimum decimation of 2) per reference
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uint8_t n = 1;
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uint32_t afe_rate_x2 = 2 * frequency;
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_base_band_frequency = frequency;
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while ((afe_rate_x2 <= MAX_AFE_RATE) && (n < MAX_N)) {
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afe_rate_x2 <<= 1;
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uint8_t n = 0;
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uint32_t afe_rate = frequency;
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// Find the largest n where AFE rate stays within limit
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// Start at n=0 and work up
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while (n < MAX_N) {
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uint32_t next_rate = afe_rate << 1;
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if (next_rate > MAX_AFE_RATE) break;
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afe_rate = next_rate;
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n++;
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}
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// Store decimation factor for potential use elsewhere
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_resampling_n = n;
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// The actual AFE rate = frequency * 2^n
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uint32_t afe_rate = frequency << n;
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// Set FPGA RX decimation register
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fpga_debug_register_write(2, n);
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radio::invalidate_spi_config();
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// Configure Si5351 clocks
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clock_generator.set_ms_frequency(0, afe_rate * 4, si5351_vco_f, 2); // CLK0: AFE_CLK
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clock_generator.set_ms_frequency(1, afe_rate * 4, si5351_vco_f, 1); // CLK1: SCT_CLK
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// CLK0: AFE_CLK (with r_div=1 for ÷2)
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// CLK1: SCT_CLK (with r_div=0 for ÷1, runs at 2× AFE for FPGA timing)
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clock_generator.set_ms_frequency(0, afe_rate * 2, si5351_vco_f, 1);
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clock_generator.set_ms_frequency(1, afe_rate * 2, si5351_vco_f, 0);
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#else
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/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
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* twice the frequency, and derived from the MS0 synth. So it's only
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