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https://github.com/portapack-mayhem/mayhem-firmware.git
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HackRF Pro (praline) arch-port initial PR (#2958)
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
This commit is contained in:
stafur
GitHub
@@ -15,13 +15,22 @@
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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#include <array>
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// Declare wrapper function. board.cpp to avoid conflicting gpio_t definitions.
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bool hackrf_r9;
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// Declare the bridge function (no need to include HackRF headers here)
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#ifdef PRALINE
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extern "C" {
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int fpga_bridge_init(void);
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}
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#endif
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/**
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* @brief PAL setup.
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@@ -262,9 +271,9 @@ const PALConfig pal_default_config = {
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{ 4, 7, scu_config_normal_drive_t { .mode=1, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* GP_CLKIN/P72/MCU_CLK: SI5351C.CLK7(O) */
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/* HackRF: LEDs. Configured early so we can use them to indicate boot status. */
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{ 4, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LED1: LED1.A(I) */
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{ 4, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LED2: LED2.A(I) */
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{ 6, 12, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LED3: LED3.A(I) */
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{ 4, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* LED1: LED1.A(I) */
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{ 4, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* LED2: LED2.A(I) */
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{ 6, 12, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* LED3: LED3.A(I) */
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/* Power control */
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{ 6, 11, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* VREGMODE/P69: TPS62410.MODE/DATA(I) */
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@@ -332,11 +341,12 @@ const PALConfig pal_default_config = {
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{ 4, 9, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SGPIO14/BANK2F3M4: CPLD.81/CPLD_P81 */
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{ 4, 10, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SGPIO15/BANK2F3M6: CPLD.78/CPLD_P78 */
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/* HackRF: CPLD */
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{ 6, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CPLD_TCK: CPLD.TCK(I), PortaPack CPLD.TCK(I) */
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{ 6, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* CPLD_TDI: CPLD.TDI(I), PortaPack I2S0_RX_SDA(O), PortaPack CPLD.TDI(I) */
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{ 6, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CPLD_TMS: CPLD.TMS(I) */
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{ 9, 5, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* CPLD_TDO: CPLD.TDO(O) */
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/* PortaPack CPLD JTAG pins - same for all builds including PRALINE
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* (PRALINE FPGA uses P5_1/P5_2/P4_10, not these pins) */
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{ 6, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CPLD_TCK: PortaPack CPLD.TCK(I) */
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{ 6, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* CPLD_TDI: PortaPack CPLD.TDI(I), I2S0_RX_SDA(O) */
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{ 6, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CPLD_TMS: HackRF CPLD.TMS(I) */
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{ 9, 5, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* CPLD_TDO: HackRF CPLD.TDO(O) */
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/* PortaPack CPLD */
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{ 1, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* SD_POW: PortaPack CPLD.TDO(O) */
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@@ -619,6 +629,10 @@ static const motocon_pwm_resources_t motocon_pwm_resources = {
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static const scu_setup_t pin_setup_vaa_enablex_pwm = { 5, 0, scu_config_normal_drive_t { .mode=1, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
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static const scu_setup_t pin_setup_vaa_enablex_gpio_og = { 5, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
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static const scu_setup_t pin_setup_vaa_enablex_gpio_r9 = { 6, 10, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
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#ifdef PRALINE
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/* PRALINE uses P8_1 (GPIO4[1]) for VAA_DISABLE (high = VAA off, low = VAA on) */
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static const scu_setup_t pin_setup_vaa_disable_praline = { 8, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
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#endif
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/* VAA powers:
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* MAX5864 analog section.
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@@ -824,7 +838,11 @@ extern "C" void __late_init(void) {
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* @todo Add your board-specific code, if any.
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*/
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extern "C" void boardInit(void) {
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#ifndef PRALINE
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/* Detect HackRF variant */
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/* 1. Perform Standard Initialization first */
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/* This configures VAA power, LED pins, and detects board revision */
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/* Let detect_hackrf_r9() run - don't force for PRALINE */
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hackrf_r9 = detect_hackrf_r9();
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/* Configure variant-dependent pins. */
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if (hackrf_r9) {
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@@ -834,12 +852,143 @@ extern "C" void boardInit(void) {
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setup_gpios(gpio_setup_og);
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setup_pins(pins_setup_og);
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}
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/* 2. Turn on VAA (Critical for Radio/Transceiver) */
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vaa_power_on();
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/* 3. Handle VAA Enable Pin Latching */
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if (hackrf_r9) {
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LPC_GPIO->W2[9] = 1;
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} else {
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LPC_GPIO->W3[6] = 1;
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}
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/* 4. HackRF Pro Specific: Initialize and Load FPGA */
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#else
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hackrf_r9 = false;
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/* Enable 3.3V aux power - P6_7 = GPIO5[15], active LOW (clear to enable) */
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LPC_SCU->SFSP[6][7] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->DIR[5] |= (1 << 15);
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LPC_GPIO->CLR[5] = (1 << 15); /* Clear = enable 3.3V aux */
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{ volatile uint32_t delay = 100000; while(delay--); }
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/* Enable 1.2V for FPGA - P8_7 = GPIO4[7], active high */
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LPC_SCU->SFSP[8][7] = 0x10;
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LPC_GPIO->DIR[4] |= (1 << 7);
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LPC_GPIO->SET[4] = (1 << 7);
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{ volatile uint32_t delay = 100000; while(delay--); }
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/* Enable VAA for RF - P8_1 = GPIO4[1], active low */
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LPC_SCU->SFSP[8][1] = 0x10;
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LPC_GPIO->DIR[4] |= (1 << 1);
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LPC_GPIO->CLR[4] = (1 << 1);
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{ volatile uint32_t delay = 100000; while(delay--); }
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/* Configure RFFC5072 pins for PRALINE */
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/* P9_2 = GPIO4[14] RFFC5072 data (SCU_GPIO_FAST | FUNCTION0 = 0xF0) */
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LPC_SCU->SFSP[9][2] = 0xF0;
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/* P9_5 = GPIO5[18] RFFC5072 clock (SCU_GPIO_FAST | FUNCTION4 = 0xF4) */
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LPC_SCU->SFSP[9][5] = 0xF4;
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LPC_GPIO->DIR[5] |= (1 << 18); /* Clock as output */
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/* Configure Port D pins for PRALINE (use SFSPD registers) */
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/* PD_14 = GPIO6[28] MAX2831 chip select */
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LPC_SCU->SFSPD[14] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->SET[6] = (1 << 28); /* CS high (inactive) */
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LPC_GPIO->DIR[6] |= (1 << 28); /* Output */
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/* PD_15 = GPIO6[29] MAX2831 RXHP control */
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LPC_SCU->SFSPD[15] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->CLR[6] = (1 << 29); /* RXHP low = 100 Hz HPF */
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LPC_GPIO->DIR[6] |= (1 << 29); /* Output */
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/* PD_16 = GPIO6[30] MAX5864 chip select */
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LPC_SCU->SFSPD[16] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->SET[6] |= (1 << 30); /* CS high (inactive) */
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LPC_GPIO->DIR[6] |= (1 << 30); /* Output */
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/* Configure Port E pins for MAX2831 control (use SFSPE registers) */
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/* PE_1 = GPIO7[1] MAX2831 ENABLE */
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LPC_SCU->SFSPE[1] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->CLR[7] = (1 << 1); /* Start disabled */
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LPC_GPIO->DIR[7] |= (1 << 1); /* Output */
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/* PE_2 = GPIO7[2] MAX2831 RXTX mode select */
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LPC_SCU->SFSPE[2] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->CLR[7] = (1 << 2); /* Start in shutdown mode */
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LPC_GPIO->DIR[7] |= (1 << 2); /* Output */
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/* Configure Port 6 pins for RF path control */
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/* P6_3 = GPIO3[2] Mixer enable (inverted: 0 = mixer ON) */
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LPC_SCU->SFSP[6][3] = 0xF0; /* SCU_GPIO_FAST | FUNCTION0 */
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LPC_GPIO->CLR[3] = (1 << 2); /* Mixer enabled by default */
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LPC_GPIO->DIR[3] |= (1 << 2); /* Output */
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/* P6_5 = GPIO3[4] TX enable */
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LPC_SCU->SFSP[6][5] = 0xF0; /* SCU_GPIO_FAST | FUNCTION0 */
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LPC_GPIO->CLR[3] = (1 << 4); /* TX off by default (RX mode) */
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LPC_GPIO->DIR[3] |= (1 << 4); /* Output */
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/* Configure Port A pins for RF path control */
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/* PA_1 = GPIO4[8] LPF enable */
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LPC_SCU->SFSP[0xA][1] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->SET[4] = (1 << 8); /* LPF enabled by default (low band) */
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LPC_GPIO->DIR[4] |= (1 << 8); /* Output */
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/* PA_2 = GPIO4[9] RF amp enable */
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LPC_SCU->SFSP[0xA][2] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
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LPC_GPIO->CLR[4] = (1 << 9); /* RF amp off by default */
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LPC_GPIO->DIR[4] |= (1 << 9); /* Output */
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/* Configure PRALINE-specific SGPIO pins for FPGA sample interface.
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* These override the HackRF One pin config from pins_setup.
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* PRALINE uses different pins than HackRF One for SGPIO4/8/9/10.
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* SCU_GPIO_FAST = 0xF0 (EPUN + EHS + EZI + ZIF)
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*/
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/* CRITICAL: Disable HackRF One SGPIO8 pin (P9_6) - PRALINE uses P8_0 instead */
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LPC_SCU->SFSP[9][6] = 0x00; /* P9_6 = GPIO mode 0, disable SGPIO function */
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/* SGPIO4 = P9_4 function 6 (HOST_DATA4) */
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LPC_SCU->SFSP[9][4] = 0xF6; /* SCU_GPIO_FAST | func 6 */
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/* SGPIO8 = P8_0 function 4 (SGPIO_CLK - clock from FPGA) */
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LPC_SCU->SFSP[8][0] = 0xF4; /* SCU_GPIO_FAST | func 4 */
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/* SGPIO9 = P9_3 function 6 (HOST_CAPTURE) */
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LPC_SCU->SFSP[9][3] = 0xF6; /* SCU_GPIO_FAST | func 6 */
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/* SGPIO10 = P8_2 function 4 (HOST_DISABLE - output to FPGA) */
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LPC_SCU->SFSP[8][2] = 0xF4; /* SCU_GPIO_FAST | func 4 */
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/* SGPIO11 = P1_17 function 6 (HOST_DIRECTION - output to FPGA, tells FPGA TX vs RX) */
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LPC_SCU->SFSP[1][17] = 0xF6; /* SCU_GPIO_FAST | func 6 */
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/* SGPIO data pins (SGPIO0-7) - all 8 bits required for sample data */
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LPC_SCU->SFSP[0][0] = 0xF3; /* SGPIO0: P0_0 function 3, HOST_DATA0 */
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LPC_SCU->SFSP[0][1] = 0xF3; /* SGPIO1: P0_1 function 3, HOST_DATA1 */
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LPC_SCU->SFSP[1][15] = 0xF2; /* SGPIO2: P1_15 function 2, HOST_DATA2 */
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LPC_SCU->SFSP[1][16] = 0xF2; /* SGPIO3: P1_16 function 2, HOST_DATA3 */
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/* SGPIO4 already configured above at line 942 */
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LPC_SCU->SFSP[6][6] = 0xF2; /* SGPIO5: P6_6 function 2, HOST_DATA5 */
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LPC_SCU->SFSP[2][2] = 0xF0; /* SGPIO6: P2_2 function 0, HOST_DATA6 */
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LPC_SCU->SFSP[1][0] = 0xF6; /* SGPIO7: P1_0 function 6, HOST_DATA7 */
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/* NOTE: P9_5 is RFFC5072 mixer clock (SCU_MIXER_SCLK), NOT SGPIO!
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* Do NOT override P9_5 here. */
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// Trigger FPGA bitstream loading via fpga bridge
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// Attempt to load the FPGA bitstream
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// This function returns LD_SUCCESS (0) if the FPGA confirms the bitstream
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// Use LEDs to check if initi is successful.
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// Setup LED pin directions
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// LED1 (USB) = GPIO2[1], LED2 (RX) = GPIO2[2], LED3 (TX) = GPIO2[8]
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LPC_GPIO->DIR[2] |= (1 << 1) | (1 << 2) | (1 << 8);
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// Turn off all LEDs to start
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// PRALINE LEDs are active-low: SET (HIGH) = OFF, CLR (LOW) = ON
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LPC_GPIO->SET[2] = (1 << 1) | (1 << 2) | (1 << 8);
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// Call fpga_bridge_init and continue boot regardless of result
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// (Watchdog was resetting device when we halted with while(1))
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int load_result = fpga_bridge_init();
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(void)load_result; // Ignore result for now, just let boot continue
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// Keep LEDs off after FPGA load
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LPC_GPIO->SET[2] = (1 << 1) | (1 << 2) | (1 << 8);
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#endif
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}
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extern "C" void _default_exit(void) {
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@@ -848,10 +997,10 @@ extern "C" void _default_exit(void) {
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} else {
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LPC_GPIO->W3[6] = 0;
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}
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vaa_power_off();
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chSysDisable();
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systick_stop();
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/* Don't reset these peripherals, as they're operating during shutdown:
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