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deadprogram
babdfc9e10
Replace movi instructions with constants outside the 12-bit signed range (-2048..2047) with movi+slli sequences. Large constants cause the assembler to emit auto-generated .literal section entries, which triggers an lld bug where l32r PC-relative offsets are miscalculated when .literal.* sections are merged with .text.* sections. Signed-off-by: deadprogram <ron@hybridgroup.com>
406 lines
12 KiB
ArmAsm
406 lines
12 KiB
ArmAsm
// Startup code for the ESP32-S3 (Xtensa LX7, windowed ABI).
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//
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// The ROM bootloader loads IRAM/DRAM segments into SRAM but does NOT
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// configure flash cache/MMU. We must:
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// 1. Set up the windowed-ABI register file and stack pointer.
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// 2. Set VECBASE and clear PS.EXCM (needed for callx4 window overflows).
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// 3. Disable watchdog timers.
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// 4. Configure the flash cache and MMU so IROM/DROM are accessible.
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// 5. Jump to runtime.main (in IROM).
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//
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// Cache/MMU init sequence (from NuttX esp_loader.c / ESP-IDF bootloader / esp-hal):
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// Phase A — configure cache modes:
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// a. rom_config_instruction_cache_mode(16KB, 8-way, 32B)
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// b. rom_Cache_Suspend_DCache()
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// c. rom_config_data_cache_mode(32KB, 8-way, 32B)
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// d. Cache_Resume_DCache(0)
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// Phase B — map flash pages:
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// e. Disable caches
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// f. Cache_MMU_Init() — reset all MMU entries to invalid
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// g. Cache_Set_IDROM_MMU_Size() — set IROM/DROM entry split
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// h. Write MMU entries mapping flash page 0 for IROM and DROM
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// i. Clear bus-shut bits
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// j. Enable caches + isync
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#define PS_WOE 0x00040000
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// -----------------------------------------------------------------------
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// Boot entry point — placed in IRAM by the linker.
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// -----------------------------------------------------------------------
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.section .text.call_start_cpu0
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.literal_position
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.align 4
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.Lstack_top_addr:
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.long _stack_top
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.Lmain_addr:
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.long main
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.Lvector_table_addr:
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.long _vector_table
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// WDT register addresses
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.Lwdt_key:
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.long 0x50D83AA1
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.Lrtc_wdt_protect:
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.long 0x600080B0
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.Lrtc_wdt_config0:
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.long 0x60008098
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.Ltimg0_wdt_protect:
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.long 0x6001F064
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.Ltimg0_wdt_config0:
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.long 0x6001F048
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.Ltimg1_wdt_protect:
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.long 0x60020064
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.Ltimg1_wdt_config0:
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.long 0x60020048
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.Lswd_protect:
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.long 0x600080B8
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.Lswd_key:
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.long 0x8F1D312A
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.Lswd_conf:
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.long 0x600080B4
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.Lswd_disable:
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.long 0x40000000
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// ROM function addresses (from ESP-IDF esp32s3.rom.ld)
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.Lrom_config_icache:
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.long 0x40001a1c
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.Lrom_config_dcache:
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.long 0x40001a28
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.Lrom_suspend_dcache:
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.long 0x400018b4
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.LCache_Resume_DCache:
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.long 0x400018c0
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.LCache_Disable_ICache:
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.long 0x4000186c
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.LCache_Disable_DCache:
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.long 0x40001884
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.LCache_MMU_Init:
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.long 0x40001998
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.LCache_Set_IDROM_MMU_Size:
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.long 0x40001914
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.LCache_Enable_ICache:
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.long 0x40001878
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.LCache_Enable_DCache:
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.long 0x40001890
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// Cache/MMU register addresses
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.Lmmu_table_base:
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.long 0x600C5000
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.Licache_ctrl1_reg:
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.long 0x600C4064
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.Ldcache_ctrl1_reg:
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.long 0x600C4004
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// End-of-section symbols for multi-page MMU mapping.
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.Lirom_end:
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.long _irom_end
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.Ldrom_end:
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.long _drom_end
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.Lirom_base:
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.long 0x42000000
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.Ldrom_base:
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.long 0x3C000000
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.global call_start_cpu0
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call_start_cpu0:
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// ---- 1. Windowed-ABI register file setup ----
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// Disable WOE (bit 18 of PS).
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// Avoid large movi constants to prevent auto-generated .literal section
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// entries, which cause l32r offset miscalculation in LLVM 22 / lld.
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rsr.ps a2
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movi a3, 1
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slli a3, a3, 18 // a3 = PS_WOE (0x40000)
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and a3, a2, a3 // isolate WOE bit
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xor a2, a2, a3 // clear WOE bit
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wsr.ps a2
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rsync
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// Set WINDOWSTART to 1 << WINDOWBASE (mark only current window as valid).
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rsr.windowbase a2
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ssl a2
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movi a2, 1
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sll a2, a2
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wsr.windowstart a2
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rsync
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// Load stack pointer.
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l32r a1, .Lstack_top_addr
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// Re-enable WOE.
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rsr.ps a2
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movi a3, 1
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slli a3, a3, 18 // a3 = PS_WOE (0x40000)
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or a2, a2, a3
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wsr.ps a2
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rsync
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// Enable FPU (coprocessor 0).
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movi a2, 1
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wsr.cpenable a2
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rsync
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// ---- 2. Disable all watchdog timers (IMMEDIATELY, before any delay) ----
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l32r a3, .Lwdt_key
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movi a4, 0
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// RTC WDT
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l32r a2, .Lrtc_wdt_protect
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memw
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s32i a3, a2, 0
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l32r a5, .Lrtc_wdt_config0
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memw
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s32i a4, a5, 0
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memw
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s32i a4, a2, 0
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// TIMG0 WDT
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l32r a2, .Ltimg0_wdt_protect
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memw
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s32i a3, a2, 0
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l32r a5, .Ltimg0_wdt_config0
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memw
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s32i a4, a5, 0
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memw
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s32i a4, a2, 0
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// TIMG1 WDT
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l32r a2, .Ltimg1_wdt_protect
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memw
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s32i a3, a2, 0
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l32r a5, .Ltimg1_wdt_config0
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memw
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s32i a4, a5, 0
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memw
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s32i a4, a2, 0
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// Super WDT
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l32r a2, .Lswd_protect
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l32r a3, .Lswd_key
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memw
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s32i a3, a2, 0
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l32r a5, .Lswd_conf
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l32r a6, .Lswd_disable
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memw
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s32i a6, a5, 0
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memw
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s32i a4, a2, 0
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// ---- 3. Set VECBASE and clear PS.EXCM ----
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// VECBASE must be set before any callx4 so that window overflow
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// exceptions (triggered by register window rotation) route to our
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// handlers in IRAM, not the ROM's default vectors.
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l32r a8, .Lvector_table_addr
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wsr.vecbase a8
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rsync
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// Clear PS.EXCM (bit 4) and PS.INTLEVEL (bits 0-3).
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// The ROM bootloader may leave EXCM=1; with EXCM set any callx4
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// window overflow would become a double exception.
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// Set PS.UM (bit 5) so level-1 exceptions route to User vector.
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rsr.ps a2
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movi a3, ~0x1F
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and a2, a2, a3
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movi a3, 0x20
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or a2, a2, a3
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wsr.ps a2
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rsync
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// ---- 4. Configure flash cache and MMU ----
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//
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// ROM function calls use callx4 (windowed ABI):
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// a4 = target address (overwritten with return addr by call mechanism)
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// a5 = stack pointer for callee (becomes callee's a1 via entry)
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// a6 = first argument (becomes callee's a2)
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// a7 = second argument (becomes callee's a3)
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// a8 = third argument (becomes callee's a4)
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// Registers a0-a3 are preserved across callx4; a4-a11 may be clobbered.
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// Phase A: Configure cache modes (required for cache hardware to function).
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// Without this, the cache doesn't know its size/associativity/line-size
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// and cannot service flash accesses.
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// 4a. Configure ICache mode: 16KB, 8-way, 32-byte line
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// Use movi+slli to avoid auto-literal generation (lld l32r bug).
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movi a6, 1
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slli a6, a6, 14 // a6 = 0x4000 = 16KB
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movi a7, 8 // ways = 8
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movi a8, 32 // line_size = 32
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mov a5, a1
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l32r a4, .Lrom_config_icache
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callx4 a4
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// 4b. Suspend DCache before configuring it
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mov a5, a1
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l32r a4, .Lrom_suspend_dcache
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callx4 a4
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// 4c. Configure DCache mode: 32KB, 8-way, 32-byte line
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movi a6, 1
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slli a6, a6, 15 // a6 = 0x8000 = 32KB
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movi a7, 8 // ways = 8
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movi a8, 32 // line_size = 32
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mov a5, a1
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l32r a4, .Lrom_config_dcache
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callx4 a4
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// 4d. Resume DCache
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movi a6, 0
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mov a5, a1
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l32r a4, .LCache_Resume_DCache
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callx4 a4
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// Phase B: Map flash pages into MMU.
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// 4e. Disable ICache
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mov a5, a1
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l32r a4, .LCache_Disable_ICache
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callx4 a4
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// 4f. Disable DCache
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mov a5, a1
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l32r a4, .LCache_Disable_DCache
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callx4 a4
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// 4g. Initialize MMU (resets all 512 entries to invalid = 0x4000)
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mov a5, a1
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l32r a4, .LCache_MMU_Init
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callx4 a4
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// 4h. Set IDROM MMU size: even 256/256 split.
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// Each entry is 4 bytes, so 256 entries = 0x400 bytes per region.
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movi a6, 0x400 // irom_mmu_size (256 entries × 4 bytes)
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movi a7, 0x400 // drom_mmu_size (256 entries × 4 bytes)
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mov a5, a1
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l32r a4, .LCache_Set_IDROM_MMU_Size
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callx4 a4
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// 4i. Map flash pages for IROM and DROM using identity mapping.
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// MMU table at 0x600C5000: entries 0-255 = ICache, 256-511 = DCache.
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// Entry value N = flash page N (SOC_MMU_VALID = 0 on S3).
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// Each 64KB page needs one 4-byte entry.
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//
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// IROM: map pages 0..N where N = (_irom_end - 0x42000000) >> 16
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// DROM: map pages 0..M where M = (_drom_end - 0x3C000000) >> 16
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l32r a8, .Lmmu_table_base // a8 = 0x600C5000
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// --- IROM pages ---
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l32r a2, .Lirom_end // a2 = _irom_end (VMA in 0x42xxxxxx)
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l32r a3, .Lirom_base // a3 = 0x42000000
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sub a2, a2, a3 // a2 = byte offset past IROM base
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srli a2, a2, 16 // a2 = last page index
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addi a2, a2, 1 // a2 = number of pages to map
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movi a9, 0 // a9 = page counter (and entry value)
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mov a10, a8 // a10 = current MMU entry pointer
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.Lirom_loop:
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s32i a9, a10, 0
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addi a9, a9, 1
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addi a10, a10, 4
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blt a9, a2, .Lirom_loop
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// --- DROM pages ---
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l32r a2, .Ldrom_end // a2 = _drom_end (VMA in 0x3Cxxxxxx)
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l32r a3, .Ldrom_base // a3 = 0x3C000000
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sub a2, a2, a3 // a2 = byte offset past DROM base
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srli a2, a2, 16 // a2 = last page index
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addi a2, a2, 1 // a2 = number of pages to map
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movi a9, 0 // a9 = page counter (and entry value)
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addmi a10, a8, 0x400 // a10 = 0x600C5400 (DCache entry 256)
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.Ldrom_loop:
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s32i a9, a10, 0
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addi a9, a9, 1
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addi a10, a10, 4
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blt a9, a2, .Ldrom_loop
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memw
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// 4j. Clear bus-shut bits so core 0 can access ICache and DCache buses.
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l32r a8, .Licache_ctrl1_reg // 0x600C4064
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movi a9, 0
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s32i a9, a8, 0 // Clear all ICACHE_CTRL1 shut bits
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l32r a8, .Ldcache_ctrl1_reg // 0x600C4004
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s32i a9, a8, 0 // Clear all DCACHE_CTRL1 shut bits
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memw
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// 4k. Enable ICache (arg: autoload = 0)
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movi a6, 0
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mov a5, a1
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l32r a4, .LCache_Enable_ICache
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callx4 a4
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// 4l. Enable DCache (arg: autoload = 0)
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movi a6, 0
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mov a5, a1
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l32r a4, .LCache_Enable_DCache
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callx4 a4
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// Flush instruction pipeline so new cache/MMU config takes effect.
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isync
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// ---- 5. Jump to main (in IROM) ----
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// Re-clear PS.EXCM in case ROM calls changed processor state.
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rsr.ps a2
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movi a3, ~0x1F
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and a2, a2, a3
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movi a3, 0x20
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or a2, a2, a3
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wsr.ps a2
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rsync
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mov a5, a1
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l32r a4, .Lmain_addr
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callx4 a4
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// If main returns, loop forever.
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1: j 1b
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// -----------------------------------------------------------------------
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// tinygo_scanCurrentStack — Spill all Xtensa register windows to the
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// stack, then call tinygo_scanstack(sp) so the conservative GC can
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// discover live heap pointers that are currently in physical registers.
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//
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// On RISC-V / ARM the equivalent function pushes callee-saved registers
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// before the call. On Xtensa windowed ABI the same effect is achieved
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// by forcing hardware window-overflow for every occupied pane: each
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// overflow saves the four registers in that pane to the stack frame
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// pointed to by the pane's a1 (sp). After all panes are flushed, a
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// scan from the current sp to stackTop covers every live value.
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// -----------------------------------------------------------------------
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.section .text.tinygo_scanCurrentStack
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.global tinygo_scanCurrentStack
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tinygo_scanCurrentStack:
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entry a1, 48
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// Disable interrupts while flushing register windows.
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rsr a4, PS
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s32i a4, a1, 0 // save PS for later restore
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rsil a4, 3 // XCHAL_EXCM_LEVEL
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// Flush all register windows using recursive call4.
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// For NAREG=64 (16 panes), 15 recursive levels cover all panes
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// except the current one (which is kept active).
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movi a6, 15
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call4 .Lscan_spill
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// Restore interrupts.
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l32i a4, a1, 0
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wsr.ps a4
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rsync
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// Pass current sp to tinygo_scanstack.
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// call4 maps caller's a5→callee's a1 (stack ptr for callee's entry)
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// and caller's a6→callee's a2 (first argument = sp).
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mov a5, a1 // callee's a1 = valid stack pointer
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mov a6, a1 // callee's a2 = sp argument
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call4 tinygo_scanstack
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retw
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.balign 4
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.Lscan_spill:
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entry a1, 16
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beqz a2, .Lscan_spill_done
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addi a2, a2, -1
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mov a6, a2
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call4 .Lscan_spill
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.Lscan_spill_done:
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retw
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