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deadprogram
4c3680635e
The UART handleInterrupt handler unconditionally read RDR on every interrupt without checking which flag triggered it. On newer STM32 USART peripherals (U5, L4, L5, L0, G0, F7, WL), RXNEIE enables interrupts for both RXFNE (data ready) and ORE (overrun error). Unlike older families (F1, F4), ORE is not cleared by reading the data register, it must be explicitly cleared via the ICR register. When an overrun occurred (e.g. serial data arriving while ADC busy-waits in Get()), ORE would trigger the interrupt, the handler would fire without clearing it, and the interrupt would re-trigger immediately, causing an infinite interrupt storm that locks up the CPU. Fix by: - Checking RXFNE/RXNE (bit 5) before reading data from RDR - Clearing ORE (bit 3) via ICR on newer peripherals when set - Adding errClearReg field to UART struct, set to &Bus.ICR in setRegisters() for all ICR-capable families - Preserving the SR+DR clearing sequence for older F1/F4 families Signed-off-by: deadprogram <ron@hybridgroup.com>
111 lines
3.0 KiB
Go
111 lines
3.0 KiB
Go
//go:build stm32
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package machine
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// Peripheral abstraction layer for UARTs on the stm32 family (except stm32g0).
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import (
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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// UART representation
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type UART struct {
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Buffer *RingBuffer
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Bus *stm32.USART_Type
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Interrupt interrupt.Interrupt
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TxAltFuncSelector uint8
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RxAltFuncSelector uint8
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// Registers specific to the chip
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rxReg *volatile.Register32
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txReg *volatile.Register32
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statusReg *volatile.Register32
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txEmptyFlag uint32
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// errClearReg points to the ICR register on newer STM32 USART peripherals
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// (L0, L4, L5, G0, F7, U5, WL, etc.) for clearing error flags. Nil for
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// older peripherals (F1, F4) where errors are cleared by reading SR+DR.
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errClearReg *volatile.Register32
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}
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// Configure the UART.
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func (uart *UART) Configure(config UARTConfig) {
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// Default baud rate to 115200.
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if config.BaudRate == 0 {
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config.BaudRate = 115200
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}
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// Set the GPIO pins to defaults if they're not set
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if config.TX == 0 && config.RX == 0 {
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config.TX = UART_TX_PIN
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config.RX = UART_RX_PIN
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}
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// STM32 families have different, but compatible, registers for
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// basic UART functions. For each family populate the registers
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// into `uart`.
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uart.setRegisters()
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// Enable USART clock
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enableAltFuncClock(unsafe.Pointer(uart.Bus))
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uart.configurePins(config)
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// Set baud rate
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uart.SetBaudRate(config.BaudRate)
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// Enable USART port, tx, rx and rx interrupts
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uart.Bus.CR1.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE)
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// Enable RX IRQ
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uart.Interrupt.SetPriority(0xc0)
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uart.Interrupt.Enable()
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}
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// handleInterrupt should be called from the appropriate interrupt handler for
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// this UART instance.
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func (uart *UART) handleInterrupt(interrupt.Interrupt) {
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s := uart.statusReg.Get()
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// Only read data when RXNE/RXFNE (bit 5) is set. On all STM32 families,
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// RXNEIE enables both the RX-data-ready and overrun-error (ORE) interrupts.
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// Without this check, an ORE-only interrupt reads garbage from RDR.
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if s&0x20 != 0 { // RXNE / RXFNE
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uart.Receive(byte((uart.rxReg.Get() & 0xFF)))
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}
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// Clear overrun error (ORE, bit 3) to prevent an interrupt storm.
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if s&0x8 != 0 {
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if uart.errClearReg != nil {
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// Newer USART peripherals: clear ORE via the ICR register.
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uart.errClearReg.Set(0x8) // ORECF
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} else if s&0x20 == 0 {
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// Older USART (F1/F4): ORE is cleared by reading SR then DR.
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// SR was already read above. If RXNE was set, DR was read in
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// the Receive path. Otherwise do a dummy DR read to complete
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// the clearing sequence.
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uart.rxReg.Get()
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}
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}
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}
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// SetBaudRate sets the communication speed for the UART. Defer to chip-specific
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// routines for calculation
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func (uart *UART) SetBaudRate(br uint32) {
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divider := uart.getBaudRateDivisor(br)
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uart.Bus.BRR.Set(divider)
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}
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// WriteByte writes a byte of data to the UART.
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func (uart *UART) writeByte(c byte) error {
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uart.txReg.Set(uint32(c))
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for !uart.statusReg.HasBits(uart.txEmptyFlag) {
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}
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return nil
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}
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func (uart *UART) flush() {}
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