deadprogram b81a7c2bca fix: ESP32-C3 needs to clear MCAUSE after handling interrupt ...

MCAUSE was never being cleared after handling an interrupt.
On RISC-V, mret does NOT zero MCAUSE — it retains the last
trap cause. Every other TinyGo RISC-V target (FE310, K210,
QEMU) explicitly does riscv.MCAUSE.Set(0) after handling.
The ESP32-C3 was missing this.

Signed-off-by: deadprogram <ron@hybridgroup.com>

2026-04-05 14:15:40 +02:00

..

crypto

machine: implement RNG for esp32s3 based on the onboard hardware random number generator.

2026-04-05 14:15:40 +02:00

device

machine: fix deprecated AsmFull comment (#5005)

2025-10-04 11:19:01 +02:00

examples

usb/cdc: Better ring buffer implementation (#5209)

2026-04-05 14:15:40 +02:00

internal

reflect: add TypeAssert

2026-01-08 21:40:42 +00:00

machine

esp32c3/esp32s3: refactoring and corrections for SPI implementation

2026-04-05 14:15:40 +02:00

net @ bb43b40f19

net: update submodule to latest commits

2025-09-19 13:14:12 +02:00

os

feat: Implement Lchown function for changing file ownership (#5161)

2026-01-10 09:31:22 +01:00

reflect

reflect: add TypeAssert

2026-01-08 21:40:42 +00:00

runtime

fix: ESP32-C3 needs to clear MCAUSE after handling interrupt

2026-04-05 14:15:40 +02:00

sync

sync: add WaitGroup.Go

2026-01-07 20:01:42 +00:00

syscall

feat: Implement Lchown function for changing file ownership (#5161)

2026-01-10 09:31:22 +01:00

testing

src/testing: add b.ReportMetric()

2026-01-09 11:17:53 +00:00

tinygo

compiler, runtime: move constants into shared package

2024-11-15 10:11:57 +01:00

unique

unique: implement custom version of unique package

2024-08-17 11:49:14 +02:00