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Konstantin Sharlaimov
5f02d6b659
Define the board's external crystal (HSE) frequency `xtalHz` in the respective `board_*.go` files. Per-topology PLL tables (F1, F4, F7) will compute the register dividers from it. Moving this parameter to the board definition level cleanly isolates board hardware characteristics from general MCU chip configurations, eliminating the need for custom target build tags. Targets using HSE-clocked STM32 chips must define `xtalHz` or fail to build.
30 lines
892 B
Go
30 lines
892 B
Go
//go:build stm32f4 && stm32f469
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package runtime
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import (
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"device/stm32"
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"machine"
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)
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/*
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clock settings
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+-------------+--------------------------------+
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| HSE | selectable (xtal_8/12/16_mhz) |
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| SYSCLK | 180mhz |
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| HCLK | 180mhz |
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| APB2(PCLK2) | 90mhz |
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| APB1(PCLK1) | 45mhz |
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+-------------+--------------------------------+
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*/
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const HSE_STARTUP_TIMEOUT = 0x0500
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// pllCFGR builds the RCC_PLLCFGR value for the current xtal - see RM0386
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// Reference Manual pg. 148.
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func pllCFGR() uint32 {
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pll := machine.PLLParams180MHz()
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return pll.M | (pll.N << stm32.RCC_PLLCFGR_PLLN_Pos) | (((pll.P >> 1) - 1) << stm32.RCC_PLLCFGR_PLLP_Pos) |
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(1 << stm32.RCC_PLLCFGR_PLLSRC_Pos) | (pll.Q << stm32.RCC_PLLCFGR_PLLQ_Pos) | (pll.R << stm32.RCC_PLLCFGR_PLLR_Pos)
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}
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