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deadprogram
aaf6a36c55
The ESP32-S3 ROM bootloader loads IRAM/DRAM into SRAM but does not configure the flash cache or MMU. Previously the target incorrectly reused the ESP32 boot assembly (esp32.S) which lacks flash XIP support. Add a dedicated esp32s3.S boot assembly that: - Sets up windowed-ABI registers, stack, and FPU - Disables all watchdog timers (RTC, TIMG0, TIMG1, Super WDT) - Configures VECBASE and clears PS.EXCM before any callx4 - Calls ROM functions to configure cache modes: rom_config_instruction_cache_mode (16KB, 8-way, 32B line) rom_config_data_cache_mode (32KB, 8-way, 32B line) - Initializes MMU, maps flash page 0 for IROM and DROM, clears bus-shut bits, and enables both caches - Jumps to runtime.main in IROM (flash) Update the linker script (esp32s3.ld) to place .text and .rodata in flash-mapped regions (IROM/DROM) with proper alignment for the MMU page size. Update esp32s3-interrupts.S with proper exception vector handlers. Point esp32s3.json at the new esp32s3.S instead of esp32.S. Signed-off-by: deadprogram <ron@hybridgroup.com>