mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-10 05:53:39 +00:00
Ayke van Laethem
90fb0ee4eb
This requires support in LLVM, as AVR support is still experimental. For example, in bindings/go/build.sh, add -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR to cmake_flags.
686 lines
20 KiB
Go
686 lines
20 KiB
Go
// Automatically generated file. DO NOT EDIT.
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// Generated by gen-device.py from ATmega168PB.atdf, see http://packs.download.atmel.com/
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// +build avr,atmega168pb
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// Device information for the ATmega168PB.
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//
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package avr
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// Magic type name for the compiler.
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type __reg uint8
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// Export this magic type name.
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type RegValue = __reg
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// Some information about this device.
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const (
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DEVICE = "ATmega168PB"
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ARCH = "AVR8"
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FAMILY = "megaAVR"
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)
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// Interrupts
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const (
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IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
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IRQ_INT0 = 1 // External Interrupt Request 0
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IRQ_INT1 = 2 // External Interrupt Request 1
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IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0
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IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0
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IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1
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IRQ_WDT = 6 // Watchdog Time-out Interrupt
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IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A
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IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A
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IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow
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IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event
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IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A
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IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B
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IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow
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IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A
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IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B
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IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow
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IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
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IRQ_USART_RX = 18 // USART Rx Complete
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IRQ_USART_UDRE = 19 // USART, Data Register Empty
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IRQ_USART_TX = 20 // USART Tx Complete
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IRQ_ADC = 21 // ADC Conversion Complete
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IRQ_EE_READY = 22 // EEPROM Ready
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IRQ_ANALOG_COMP = 23 // Analog Comparator
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IRQ_TWI = 24 // Two-wire Serial Interface
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IRQ_SPM_Ready = 25 // Store Program Memory Read
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IRQ_USART_START = 26 // USART Start Edge Interrupt
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IRQ_max = 26 // Highest interrupt number on this device.
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)
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// Peripherals
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var (
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// Fuses
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FUSE = struct {
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EXTENDED __reg
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HIGH __reg
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LOW __reg
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}{
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EXTENDED: 0x2,
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HIGH: 0x1,
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LOW: 0x0,
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}
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// Lockbits
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LOCKBIT = struct {
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LOCKBIT __reg
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}{
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LOCKBIT: 0x0,
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}
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// Device ID
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DEVICEID = struct {
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DEVID0 __reg
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DEVID1 __reg
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DEVID2 __reg
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DEVID3 __reg
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DEVID4 __reg
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DEVID5 __reg
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DEVID6 __reg
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DEVID7 __reg
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DEVID8 __reg
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}{
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DEVID0: 0xf0,
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DEVID1: 0xf1,
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DEVID2: 0xf2,
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DEVID3: 0xf3,
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DEVID4: 0xf4,
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DEVID5: 0xf5,
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DEVID6: 0xf6,
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DEVID7: 0xf7,
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DEVID8: 0xf8,
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}
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// USART
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USART = struct {
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UDR0 __reg
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UCSR0A __reg
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UCSR0B __reg
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UCSR0C __reg
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UCSR0D __reg
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UBRR0L __reg
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UBRR0H __reg
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}{
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UDR0: 0xc6, // USART I/O Data Register
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UCSR0A: 0xc0, // USART Control and Status Register A
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UCSR0B: 0xc1, // USART Control and Status Register B
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UCSR0C: 0xc2, // USART Control and Status Register C
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UCSR0D: 0xc3, // USART Control and Status Register D
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UBRR0L: 0xc4, // USART Baud Rate Register Bytes
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UBRR0H: 0xc4, // USART Baud Rate Register Bytes
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}
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// Two Wire Serial Interface
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TWI = struct {
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TWAMR __reg
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TWBR __reg
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TWCR __reg
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TWSR __reg
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TWDR __reg
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TWAR __reg
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}{
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TWAMR: 0xbd, // TWI (Slave) Address Mask Register
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TWBR: 0xb8, // TWI Bit Rate register
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TWCR: 0xbc, // TWI Control Register
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TWSR: 0xb9, // TWI Status Register
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TWDR: 0xbb, // TWI Data register
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TWAR: 0xba, // TWI (Slave) Address register
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}
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// Timer/Counter, 16-bit
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TC16 = struct {
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TIMSK1 __reg
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TIFR1 __reg
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TCCR1A __reg
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TCCR1B __reg
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TCCR1C __reg
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TCNT1L __reg
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TCNT1H __reg
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OCR1AL __reg
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OCR1AH __reg
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OCR1BL __reg
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OCR1BH __reg
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ICR1L __reg
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ICR1H __reg
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}{
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TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
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TIFR1: 0x36, // Timer/Counter Interrupt Flag register
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TCCR1A: 0x80, // Timer/Counter1 Control Register A
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TCCR1B: 0x81, // Timer/Counter1 Control Register B
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TCCR1C: 0x82, // Timer/Counter1 Control Register C
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TCNT1L: 0x84, // Timer/Counter1 Bytes
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TCNT1H: 0x84, // Timer/Counter1 Bytes
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OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
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OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
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OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
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OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
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ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
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ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
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}
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// Timer/Counter, 8-bit Async
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TC8_ASYNC = struct {
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TIMSK2 __reg
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TIFR2 __reg
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TCCR2A __reg
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TCCR2B __reg
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TCNT2 __reg
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OCR2B __reg
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OCR2A __reg
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ASSR __reg
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}{
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TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
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TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
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TCCR2A: 0xb0, // Timer/Counter2 Control Register A
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TCCR2B: 0xb1, // Timer/Counter2 Control Register B
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TCNT2: 0xb2, // Timer/Counter2
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OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
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OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
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ASSR: 0xb6, // Asynchronous Status Register
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}
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// Analog-to-Digital Converter
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ADC = struct {
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ADMUX __reg
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ADCL __reg
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ADCH __reg
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ADCSRA __reg
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ADCSRB __reg
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DIDR0 __reg
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}{
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ADMUX: 0x7c, // The ADC multiplexer Selection Register
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ADCL: 0x78, // ADC Data Register Bytes
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ADCH: 0x78, // ADC Data Register Bytes
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ADCSRA: 0x7a, // The ADC Control and Status register A
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ADCSRB: 0x7b, // The ADC Control and Status register B
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DIDR0: 0x7e, // Digital Input Disable Register
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}
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// Analog Comparator
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AC = struct {
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ACSR __reg
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DIDR1 __reg
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ACSRB __reg
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}{
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ACSR: 0x50, // Analog Comparator Control And Status Register
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DIDR1: 0x7f, // Digital Input Disable Register 1
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ACSRB: 0x4f, // Analog Comparator Status Register B
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}
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// I/O Port
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PORT = struct {
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PORTB __reg
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DDRB __reg
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PINB __reg
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PORTC __reg
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DDRC __reg
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PINC __reg
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PORTD __reg
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DDRD __reg
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PIND __reg
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PORTE __reg
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DDRE __reg
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PINE __reg
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}{
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PORTB: 0x25, // Port B Data Register
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DDRB: 0x24, // Port B Data Direction Register
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PINB: 0x23, // Port B Input Pins
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PORTC: 0x28, // Port C Data Register
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DDRC: 0x27, // Port C Data Direction Register
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PINC: 0x26, // Port C Input Pins
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PORTD: 0x2b, // Port D Data Register
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DDRD: 0x2a, // Port D Data Direction Register
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PIND: 0x29, // Port D Input Pins
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PORTE: 0x2e, // Port E Data Register
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DDRE: 0x2d, // Port E Data Direction Register
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PINE: 0x2c, // Port E Input Pins
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}
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// Timer/Counter, 8-bit
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TC8 = struct {
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OCR0B __reg
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OCR0A __reg
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TCNT0 __reg
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TCCR0B __reg
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TCCR0A __reg
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TIMSK0 __reg
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TIFR0 __reg
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}{
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OCR0B: 0x48, // Timer/Counter0 Output Compare Register
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OCR0A: 0x47, // Timer/Counter0 Output Compare Register
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TCNT0: 0x46, // Timer/Counter0
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TCCR0B: 0x45, // Timer/Counter Control Register B
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TCCR0A: 0x44, // Timer/Counter Control Register A
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TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
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TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
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}
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// External Interrupts
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EXINT = struct {
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EICRA __reg
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EIMSK __reg
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EIFR __reg
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PCICR __reg
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PCMSK2 __reg
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PCMSK1 __reg
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PCMSK0 __reg
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PCIFR __reg
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}{
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EICRA: 0x69, // External Interrupt Control Register
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EIMSK: 0x3d, // External Interrupt Mask Register
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EIFR: 0x3c, // External Interrupt Flag Register
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PCICR: 0x68, // Pin Change Interrupt Control Register
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PCMSK2: 0x6d, // Pin Change Mask Register 2
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PCMSK1: 0x6c, // Pin Change Mask Register 1
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PCMSK0: 0x6b, // Pin Change Mask Register 0
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PCIFR: 0x3b, // Pin Change Interrupt Flag Register
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}
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// Serial Peripheral Interface
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SPI = struct {
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SPDR __reg
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SPSR __reg
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SPCR __reg
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}{
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SPDR: 0x4e, // SPI Data Register
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SPSR: 0x4d, // SPI Status Register
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SPCR: 0x4c, // SPI Control Register
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}
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// Watchdog Timer
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WDT = struct {
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WDTCSR __reg
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}{
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WDTCSR: 0x60, // Watchdog Timer Control Register
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}
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// EEPROM
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EEPROM = struct {
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EEARL __reg
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EEARH __reg
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EEDR __reg
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EECR __reg
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}{
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EEARL: 0x41, // EEPROM Address Register Bytes
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EEARH: 0x41, // EEPROM Address Register Bytes
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EEDR: 0x40, // EEPROM Data Register
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EECR: 0x3f, // EEPROM Control Register
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}
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// CPU Registers
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CPU = struct {
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PRR __reg
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OSCCAL __reg
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CLKPR __reg
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SREG __reg
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SPL __reg
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SPH __reg
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SPMCSR __reg
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MCUCR __reg
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MCUSR __reg
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SMCR __reg
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GPIOR2 __reg
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GPIOR1 __reg
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GPIOR0 __reg
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}{
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PRR: 0x64, // Power Reduction Register
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OSCCAL: 0x66, // Oscillator Calibration Value
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CLKPR: 0x61, // Clock Prescale Register
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SREG: 0x5f, // Status Register
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SPL: 0x5d, // Stack Pointer
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SPH: 0x5d, // Stack Pointer
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SPMCSR: 0x57, // Store Program Memory Control and Status Register
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MCUCR: 0x55, // MCU Control Register
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MCUSR: 0x54, // MCU Status Register
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SMCR: 0x53, // Sleep Mode Control Register
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GPIOR2: 0x4b, // General Purpose I/O Register 2
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GPIOR1: 0x4a, // General Purpose I/O Register 1
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GPIOR0: 0x3e, // General Purpose I/O Register 0
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}
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)
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// Bitfields for FUSE: Fuses
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const (
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// EXTENDED
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EXTENDED_BOOTSZ = 0x6 // Select boot size
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EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled
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// HIGH
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HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
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HIGH_DWEN = 0x40 // Debug Wire enable
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HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
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HIGH_WDTON = 0x10 // Watch-dog Timer always on
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HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
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HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level
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// LOW
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LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
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LOW_CKOUT = 0x40 // Clock output on PORTB0
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LOW_SUT_CKSEL = 0x3f // Select Clock Source
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)
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// Bitfields for LOCKBIT: Lockbits
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const (
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// LOCKBIT
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LOCKBIT_LB = 0x3 // Memory Lock
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LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
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LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
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)
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// Bitfields for USART: USART
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const (
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// UCSR0A: USART Control and Status Register A
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UCSR0A_RXC0 = 0x80 // USART Receive Complete
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UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
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UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
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UCSR0A_FE0 = 0x10 // Framing Error
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UCSR0A_DOR0 = 0x8 // Data overRun
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UCSR0A_UPE0 = 0x4 // Parity Error
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UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
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UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
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// UCSR0B: USART Control and Status Register B
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UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
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UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
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UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
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UCSR0B_RXEN0 = 0x10 // Receiver Enable
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UCSR0B_TXEN0 = 0x8 // Transmitter Enable
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UCSR0B_UCSZ02 = 0x4 // Character Size
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UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
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UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
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// UCSR0C: USART Control and Status Register C
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UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
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UCSR0C_UPM0 = 0x30 // Parity Mode Bits
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UCSR0C_USBS0 = 0x8 // Stop Bit Select
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UCSR0C_UCSZ0 = 0x6 // Character Size
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UCSR0C_UCPOL0 = 0x1 // Clock Polarity
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// UCSR0D: USART Control and Status Register D
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UCSR0D_RXSIE = 0x80 // RX Start Interrupt Enable
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UCSR0D_RXS = 0x40 // RX Start
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UCSR0D_SFDE = 0x20 // Start Frame Detection Enable
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)
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// Bitfields for TWI: Two Wire Serial Interface
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const (
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// TWAMR: TWI (Slave) Address Mask Register
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TWAMR_TWAM = 0xfe
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// TWCR: TWI Control Register
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TWCR_TWINT = 0x80 // TWI Interrupt Flag
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TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
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TWCR_TWSTA = 0x20 // TWI Start Condition Bit
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TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
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TWCR_TWWC = 0x8 // TWI Write Collition Flag
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TWCR_TWEN = 0x4 // TWI Enable Bit
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TWCR_TWIE = 0x1 // TWI Interrupt Enable
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// TWSR: TWI Status Register
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TWSR_TWS = 0xf8 // TWI Status
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TWSR_TWPS = 0x3 // TWI Prescaler
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// TWAR: TWI (Slave) Address register
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TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
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TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
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)
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// Bitfields for TC16: Timer/Counter, 16-bit
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const (
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// TIMSK1: Timer/Counter Interrupt Mask Register
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TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
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TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
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TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
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TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1: Timer/Counter Interrupt Flag register
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TIFR1_ICF1 = 0x20 // Input Capture Flag 1
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TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
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TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
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TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
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// TCCR1A: Timer/Counter1 Control Register A
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TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
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TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
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TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
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// TCCR1B: Timer/Counter1 Control Register B
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TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
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TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
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TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
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TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
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// TCCR1C: Timer/Counter1 Control Register C
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TCCR1C_FOC1A = 0x80
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TCCR1C_FOC1B = 0x40
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)
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// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
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const (
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// TIMSK2: Timer/Counter Interrupt Mask register
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TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
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TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
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TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
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// TIFR2: Timer/Counter Interrupt Flag Register
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TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
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TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
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TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
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// TCCR2A: Timer/Counter2 Control Register A
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TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
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TCCR2A_COM2B = 0x30 // Compare Output Mode bits
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TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
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// TCCR2B: Timer/Counter2 Control Register B
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TCCR2B_FOC2A = 0x80 // Force Output Compare A
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TCCR2B_FOC2B = 0x40 // Force Output Compare B
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TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
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TCCR2B_CS2 = 0x7 // Clock Select bits
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// ASSR: Asynchronous Status Register
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ASSR_EXCLK = 0x40 // Enable External Clock Input
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ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
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ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
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ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
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ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
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ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
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ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
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)
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// Bitfields for ADC: Analog-to-Digital Converter
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const (
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// ADMUX: The ADC multiplexer Selection Register
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ADMUX_REFS = 0xc0 // Reference Selection Bits
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ADMUX_ADLAR = 0x20 // Left Adjust Result
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ADMUX_MUX = 0xf // Analog Channel Selection Bits
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// ADCSRA: The ADC Control and Status register A
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ADCSRA_ADEN = 0x80 // ADC Enable
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ADCSRA_ADSC = 0x40 // ADC Start Conversion
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ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
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ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
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ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
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ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
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// ADCSRB: The ADC Control and Status register B
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ADCSRB_ACME = 0x40
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ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits
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// DIDR0: Digital Input Disable Register
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DIDR0_ADC5D = 0x20
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DIDR0_ADC4D = 0x10
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DIDR0_ADC3D = 0x8
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DIDR0_ADC2D = 0x4
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DIDR0_ADC1D = 0x2
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DIDR0_ADC0D = 0x1
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)
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// Bitfields for AC: Analog Comparator
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const (
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// ACSR: Analog Comparator Control And Status Register
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ACSR_ACD = 0x80 // Analog Comparator Disable
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ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
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ACSR_ACO = 0x20 // Analog Compare Output
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ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
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ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
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ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
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ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
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// DIDR1: Digital Input Disable Register 1
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DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
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DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
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// ACSRB: Analog Comparator Status Register B
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ACSRB_ACOE = 0x1 // Analog Comparator Output Enable
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)
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// Bitfields for TC8: Timer/Counter, 8-bit
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const (
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// TCCR0B: Timer/Counter Control Register B
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TCCR0B_FOC0A = 0x80 // Force Output Compare A
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TCCR0B_FOC0B = 0x40 // Force Output Compare B
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TCCR0B_WGM02 = 0x8
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TCCR0B_CS0 = 0x7 // Clock Select
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// TCCR0A: Timer/Counter Control Register A
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TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
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TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
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TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
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// TIMSK0: Timer/Counter0 Interrupt Mask Register
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TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
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TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
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TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0: Timer/Counter0 Interrupt Flag register
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TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
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TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
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TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
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)
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// Bitfields for EXINT: External Interrupts
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const (
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// EICRA: External Interrupt Control Register
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EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
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EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
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// EIMSK: External Interrupt Mask Register
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EIMSK_INT = 0x3 // External Interrupt Request 1 Enable
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// EIFR: External Interrupt Flag Register
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EIFR_INTF = 0x3 // External Interrupt Flags
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// PCICR: Pin Change Interrupt Control Register
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PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
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// PCMSK2: Pin Change Mask Register 2
|
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PCMSK2_PCINT = 0xff // Pin Change Enable Masks
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// PCMSK1: Pin Change Mask Register 1
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PCMSK1_PCINT = 0x7f // Pin Change Enable Masks
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// PCMSK0: Pin Change Mask Register 0
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PCMSK0_PCINT = 0xff // Pin Change Enable Masks
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|
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// PCIFR: Pin Change Interrupt Flag Register
|
|
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
|
)
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// Bitfields for SPI: Serial Peripheral Interface
|
|
const (
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// SPSR: SPI Status Register
|
|
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
|
SPSR_WCOL = 0x40 // Write Collision Flag
|
|
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
|
|
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// SPCR: SPI Control Register
|
|
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
|
SPCR_SPE = 0x40 // SPI Enable
|
|
SPCR_DORD = 0x20 // Data Order
|
|
SPCR_MSTR = 0x10 // Master/Slave Select
|
|
SPCR_CPOL = 0x8 // Clock polarity
|
|
SPCR_CPHA = 0x4 // Clock Phase
|
|
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
|
)
|
|
|
|
// Bitfields for WDT: Watchdog Timer
|
|
const (
|
|
// WDTCSR: Watchdog Timer Control Register
|
|
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
|
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
|
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
|
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
|
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
|
)
|
|
|
|
// Bitfields for EEPROM: EEPROM
|
|
const (
|
|
// EECR: EEPROM Control Register
|
|
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
|
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
|
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
|
EECR_EEPE = 0x2 // EEPROM Write Enable
|
|
EECR_EERE = 0x1 // EEPROM Read Enable
|
|
)
|
|
|
|
// Bitfields for CPU: CPU Registers
|
|
const (
|
|
// PRR: Power Reduction Register
|
|
PRR_PRTWI = 0x80 // Power Reduction TWI
|
|
PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
|
PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
|
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
|
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
|
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
|
PRR_PRADC = 0x1 // Power Reduction ADC
|
|
|
|
// OSCCAL: Oscillator Calibration Value
|
|
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
|
|
|
// CLKPR: Clock Prescale Register
|
|
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
|
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
|
|
|
// SREG: Status Register
|
|
SREG_I = 0x80 // Global Interrupt Enable
|
|
SREG_T = 0x40 // Bit Copy Storage
|
|
SREG_H = 0x20 // Half Carry Flag
|
|
SREG_S = 0x10 // Sign Bit
|
|
SREG_V = 0x8 // Two's Complement Overflow Flag
|
|
SREG_N = 0x4 // Negative Flag
|
|
SREG_Z = 0x2 // Zero Flag
|
|
SREG_C = 0x1 // Carry Flag
|
|
|
|
// SPMCSR: Store Program Memory Control and Status Register
|
|
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
|
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
|
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
|
SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable
|
|
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
|
SPMCSR_PGWRT = 0x4 // Page Write
|
|
SPMCSR_PGERS = 0x2 // Page Erase
|
|
SPMCSR_SPMEN = 0x1 // Store Program Memory
|
|
|
|
// MCUCR: MCU Control Register
|
|
MCUCR_BODS = 0x40 // BOD Sleep
|
|
MCUCR_BODSE = 0x20 // BOD Sleep Enable
|
|
MCUCR_PUD = 0x10
|
|
MCUCR_IVSEL = 0x2
|
|
MCUCR_IVCE = 0x1
|
|
|
|
// MCUSR: MCU Status Register
|
|
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
|
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
|
MCUSR_EXTRF = 0x2 // External Reset Flag
|
|
MCUSR_PORF = 0x1 // Power-on reset flag
|
|
|
|
// SMCR: Sleep Mode Control Register
|
|
SMCR_SM = 0xe // Sleep Mode Select Bits
|
|
SMCR_SE = 0x1 // Sleep Enable
|
|
)
|