tinygo-org/tinygo
1
0
Fork 0
mirror of https://github.com/tinygo-org/tinygo.git synced 2026-08-11 06:23:39 +00:00
Code Issues Packages Projects Releases 6 Wiki Activity
Files
90fb0ee4eb321b5c692269ed85843cfb7540ba03
tinygo/src/device/avr/at90can128.go
T
Ayke van Laethem 90fb0ee4eb Add AVR support 
This requires support in LLVM, as AVR support is still experimental. For
example, in bindings/go/build.sh, add
-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR to cmake_flags.
2018-06-07 18:35:54 +02:00

1001 lines
32 KiB
Go
Raw Blame History

// Automatically generated file. DO NOT EDIT.
// Generated by gen-device.py from AT90CAN128.atdf, see http://packs.download.atmel.com/
// +build avr,at90can128
// Device information for the AT90CAN128.
//
package avr
// Magic type name for the compiler.
type __reg uint8
// Export this magic type name.
type RegValue = __reg
// Some information about this device.
const (
DEVICE = "AT90CAN128"
ARCH = "AVR8"
FAMILY = "megaAVR"
)
// Interrupts
const (
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
IRQ_INT0 = 1 // External Interrupt Request 0
IRQ_INT1 = 2 // External Interrupt Request 1
IRQ_INT2 = 3 // External Interrupt Request 2
IRQ_INT3 = 4 // External Interrupt Request 3
IRQ_INT4 = 5 // External Interrupt Request 4
IRQ_INT5 = 6 // External Interrupt Request 5
IRQ_INT6 = 7 // External Interrupt Request 6
IRQ_INT7 = 8 // External Interrupt Request 7
IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match
IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
IRQ_TIMER1_COMPC = 14 // Timer/Counter1 Compare Match C
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
IRQ_TIMER0_COMP = 16 // Timer/Counter0 Compare Match
IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow
IRQ_CANIT = 18 // CAN Transfer Complete or Error
IRQ_OVRIT = 19 // CAN Timer Overrun
IRQ_SPI_STC = 20 // SPI Serial Transfer Complete
IRQ_USART0_RX = 21 // USART0, Rx Complete
IRQ_USART0_UDRE = 22 // USART0 Data Register Empty
IRQ_USART0_TX = 23 // USART0, Tx Complete
IRQ_ANALOG_COMP = 24 // Analog Comparator
IRQ_ADC = 25 // ADC Conversion Complete
IRQ_EE_READY = 26 // EEPROM Ready
IRQ_TIMER3_CAPT = 27 // Timer/Counter3 Capture Event
IRQ_TIMER3_COMPA = 28 // Timer/Counter3 Compare Match A
IRQ_TIMER3_COMPB = 29 // Timer/Counter3 Compare Match B
IRQ_TIMER3_COMPC = 30 // Timer/Counter3 Compare Match C
IRQ_TIMER3_OVF = 31 // Timer/Counter3 Overflow
IRQ_USART1_RX = 32 // USART1, Rx Complete
IRQ_USART1_UDRE = 33 // USART1, Data Register Empty
IRQ_USART1_TX = 34 // USART1, Tx Complete
IRQ_TWI = 35 // 2-wire Serial Interface
IRQ_SPM_READY = 36 // Store Program Memory Read
IRQ_max = 36 // Highest interrupt number on this device.
)
// Peripherals
var (
// Fuses
FUSE = struct {
EXTENDED __reg
HIGH __reg
LOW __reg
}{
EXTENDED: 0x2,
HIGH: 0x1,
LOW: 0x0,
}
// Lockbits
LOCKBIT = struct {
LOCKBIT __reg
}{
LOCKBIT: 0x0,
}
// I/O Port
PORT = struct {
PORTA __reg
DDRA __reg
PINA __reg
PORTB __reg
DDRB __reg
PINB __reg
PORTC __reg
DDRC __reg
PINC __reg
PORTD __reg
DDRD __reg
PIND __reg
PORTE __reg
DDRE __reg
PINE __reg
PORTF __reg
DDRF __reg
PINF __reg
PORTG __reg
DDRG __reg
PING __reg
}{
PORTA: 0x22, // Port A Data Register
DDRA: 0x21, // Port A Data Direction Register
PINA: 0x20, // Port A Input Pins
PORTB: 0x25, // Port B Data Register
DDRB: 0x24, // Port B Data Direction Register
PINB: 0x23, // Port B Input Pins
PORTC: 0x28, // Port C Data Register
DDRC: 0x27, // Port C Data Direction Register
PINC: 0x26, // Port C Input Pins
PORTD: 0x2b, // Port D Data Register
DDRD: 0x2a, // Port D Data Direction Register
PIND: 0x29, // Port D Input Pins
PORTE: 0x2e, // Data Register, Port E
DDRE: 0x2d, // Data Direction Register, Port E
PINE: 0x2c, // Input Pins, Port E
PORTF: 0x31, // Data Register, Port F
DDRF: 0x30, // Data Direction Register, Port F
PINF: 0x2f, // Input Pins, Port F
PORTG: 0x34, // Data Register, Port G
DDRG: 0x33, // Data Direction Register, Port G
PING: 0x32, // Input Pins, Port G
}
// JTAG Interface
JTAG = struct {
OCDR __reg
}{
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
}
// Serial Peripheral Interface
SPI = struct {
SPCR __reg
SPSR __reg
SPDR __reg
}{
SPCR: 0x4c, // SPI Control Register
SPSR: 0x4d, // SPI Status Register
SPDR: 0x4e, // SPI Data Register
}
// Two Wire Serial Interface
TWI = struct {
TWBR __reg
TWCR __reg
TWSR __reg
TWDR __reg
TWAR __reg
}{
TWBR: 0xb8, // TWI Bit Rate register
TWCR: 0xbc, // TWI Control Register
TWSR: 0xb9, // TWI Status Register
TWDR: 0xbb, // TWI Data register
TWAR: 0xba, // TWI (Slave) Address register
}
// USART
USART = struct {
UDR0 __reg
UCSR0A __reg
UCSR0B __reg
UCSR0C __reg
UBRR0L __reg
UBRR0H __reg
UDR1 __reg
UCSR1A __reg
UCSR1B __reg
UCSR1C __reg
UBRR1L __reg
UBRR1H __reg
}{
UDR0: 0xc6, // USART I/O Data Register
UCSR0A: 0xc0, // USART Control and Status Register A
UCSR0B: 0xc1, // USART Control and Status Register B
UCSR0C: 0xc2, // USART Control and Status Register C
UBRR0L: 0xc4, // USART Baud Rate Register t Bytes
UBRR0H: 0xc4, // USART Baud Rate Register t Bytes
UDR1: 0xce, // USART I/O Data Register
UCSR1A: 0xc8, // USART Control and Status Register A
UCSR1B: 0xc9, // USART Control and Status Register B
UCSR1C: 0xca, // USART Control and Status Register C
UBRR1L: 0xcc, // USART Baud Rate Register t Bytes
UBRR1H: 0xcc, // USART Baud Rate Register t Bytes
}
// CPU Registers
CPU = struct {
SREG __reg
SPL __reg
SPH __reg
XMCRA __reg
XMCRB __reg
OSCCAL __reg
CLKPR __reg
SMCR __reg
RAMPZ __reg
GPIOR2 __reg
GPIOR1 __reg
GPIOR0 __reg
}{
SREG: 0x5f, // Status Register
SPL: 0x5d, // Stack Pointer
SPH: 0x5d, // Stack Pointer
XMCRA: 0x74, // External Memory Control Register A
XMCRB: 0x75, // External Memory Control Register B
OSCCAL: 0x66, // Oscillator Calibration Value
CLKPR: 0x61, // Clock Prescale Register
SMCR: 0x53, // Sleep Mode Control Register
RAMPZ: 0x5b, // RAM Page Z Select Register
GPIOR2: 0x4b, // General Purpose IO Register 2
GPIOR1: 0x4a, // General Purpose IO Register 1
GPIOR0: 0x3e, // General Purpose IO Register 0
}
// Bootloader
BOOT_LOAD = struct {
SPMCSR __reg
}{
SPMCSR: 0x57, // Store Program Memory Control Register
}
// External Interrupts
EXINT = struct {
EICRA __reg
EICRB __reg
EIMSK __reg
EIFR __reg
}{
EICRA: 0x69, // External Interrupt Control Register A
EICRB: 0x6a, // External Interrupt Control Register B
EIMSK: 0x3d, // External Interrupt Mask Register
EIFR: 0x3c, // External Interrupt Flag Register
}
// EEPROM
EEPROM = struct {
EEARL __reg
EEARH __reg
EEDR __reg
EECR __reg
}{
EEARL: 0x41, // EEPROM Read/Write Access Bytes
EEARH: 0x41, // EEPROM Read/Write Access Bytes
EEDR: 0x40, // EEPROM Data Register
EECR: 0x3f, // EEPROM Control Register
}
// Timer/Counter, 8-bit
TC8 = struct {
TCCR0A __reg
TCNT0 __reg
OCR0A __reg
TIMSK0 __reg
TIFR0 __reg
}{
TCCR0A: 0x44, // Timer/Counter0 Control Register
TCNT0: 0x46, // Timer/Counter0
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
}
// Timer/Counter, 16-bit
TC16 = struct {
TCCR1A __reg
TCCR1B __reg
TCCR1C __reg
TCNT1L __reg
TCNT1H __reg
OCR1AL __reg
OCR1AH __reg
OCR1BL __reg
OCR1BH __reg
OCR1CL __reg
OCR1CH __reg
ICR1L __reg
ICR1H __reg
TIMSK1 __reg
TIFR1 __reg
TCCR3A __reg
TCCR3B __reg
TCCR3C __reg
TCNT3L __reg
TCNT3H __reg
OCR3AL __reg
OCR3AH __reg
OCR3BL __reg
OCR3BH __reg
OCR3CL __reg
OCR3CH __reg
ICR3L __reg
ICR3H __reg
TIMSK3 __reg
TIFR3 __reg
}{
TCCR1A: 0x80, // Timer/Counter1 Control Register A
TCCR1B: 0x81, // Timer/Counter1 Control Register B
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
TCNT1L: 0x84, // Timer/Counter1 Bytes
TCNT1H: 0x84, // Timer/Counter1 Bytes
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register Bytes
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register Bytes
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
TCCR3A: 0x90, // Timer/Counter3 Control Register A
TCCR3B: 0x91, // Timer/Counter3 Control Register B
TCCR3C: 0x92, // Timer/Counter 3 Control Register C
TCNT3L: 0x94, // Timer/Counter3 Bytes
TCNT3H: 0x94, // Timer/Counter3 Bytes
OCR3AL: 0x98, // Timer/Counter3 Output Compare Register Bytes
OCR3AH: 0x98, // Timer/Counter3 Output Compare Register Bytes
OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register Bytes
OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register Bytes
OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register Bytes
OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register Bytes
ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes
ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes
TIMSK3: 0x71, // Timer/Counter Interrupt Mask Register
TIFR3: 0x38, // Timer/Counter Interrupt Flag register
}
// Timer/Counter, 8-bit Async
TC8_ASYNC = struct {
TCCR2A __reg
TCNT2 __reg
OCR2A __reg
TIMSK2 __reg
TIFR2 __reg
ASSR __reg
}{
TCCR2A: 0xb0, // Timer/Counter2 Control Register
TCNT2: 0xb2, // Timer/Counter2
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
ASSR: 0xb6, // Asynchronous Status Register
}
// Watchdog Timer
WDT = struct {
WDTCR __reg
}{
WDTCR: 0x60, // Watchdog Timer Control Register
}
// Analog-to-Digital Converter
ADC = struct {
ADMUX __reg
ADCSRA __reg
ADCL __reg
ADCH __reg
DIDR0 __reg
}{
ADMUX: 0x7c, // The ADC multiplexer Selection Register
ADCSRA: 0x7a, // The ADC Control and Status register
ADCL: 0x78, // ADC Data Register Bytes
ADCH: 0x78, // ADC Data Register Bytes
DIDR0: 0x7e, // Digital Input Disable Register 1
}
// Analog Comparator
AC = struct {
ACSR __reg
DIDR1 __reg
}{
ACSR: 0x50, // Analog Comparator Control And Status Register
DIDR1: 0x7f,
}
// Controller Area Network
CAN = struct {
CANGCON __reg
CANGSTA __reg
CANGIT __reg
CANGIE __reg
CANEN2 __reg
CANEN1 __reg
CANIE2 __reg
CANIE1 __reg
CANSIT2 __reg
CANSIT1 __reg
CANBT1 __reg
CANBT2 __reg
CANBT3 __reg
CANTCON __reg
CANTIML __reg
CANTIMH __reg
CANTTCL __reg
CANTTCH __reg
CANTEC __reg
CANREC __reg
CANHPMOB __reg
CANPAGE __reg
CANSTMOB __reg
CANCDMOB __reg
CANIDT4 __reg
CANIDT3 __reg
CANIDT2 __reg
CANIDT1 __reg
CANIDM4 __reg
CANIDM3 __reg
CANIDM2 __reg
CANIDM1 __reg
CANSTML __reg
CANSTMH __reg
CANMSG __reg
}{
CANGCON: 0xd8, // CAN General Control Register
CANGSTA: 0xd9, // CAN General Status Register
CANGIT: 0xda, // CAN General Interrupt Register
CANGIE: 0xdb, // CAN General Interrupt Enable Register
CANEN2: 0xdc, // Enable MOb Register
CANEN1: 0xdd, // Enable MOb Register
CANIE2: 0xde, // Enable Interrupt MOb Register
CANIE1: 0xdf, // Enable Interrupt MOb Register
CANSIT2: 0xe0, // CAN Status Interrupt MOb Register
CANSIT1: 0xe1, // CAN Status Interrupt MOb Register
CANBT1: 0xe2, // Bit Timing Register 1
CANBT2: 0xe3, // Bit Timing Register 2
CANBT3: 0xe4, // Bit Timing Register 3
CANTCON: 0xe5, // Timer Control Register
CANTIML: 0xe6, // Timer Register
CANTIMH: 0xe6, // Timer Register
CANTTCL: 0xe8, // TTC Timer Register
CANTTCH: 0xe8, // TTC Timer Register
CANTEC: 0xea, // Transmit Error Counter Register
CANREC: 0xeb, // Receive Error Counter Register
CANHPMOB: 0xec, // Highest Priority MOb Register
CANPAGE: 0xed, // Page MOb Register
CANSTMOB: 0xee, // MOb Status Register
CANCDMOB: 0xef, // MOb Control and DLC Register
CANIDT4: 0xf0, // Identifier Tag Register 4
CANIDT3: 0xf1, // Identifier Tag Register 3
CANIDT2: 0xf2, // Identifier Tag Register 2
CANIDT1: 0xf3, // Identifier Tag Register 1
CANIDM4: 0xf4, // Identifier Mask Register 4
CANIDM3: 0xf5, // Identifier Mask Register 3
CANIDM2: 0xf6, // Identifier Mask Register 2
CANIDM1: 0xf7, // Identifier Mask Register 1
CANSTML: 0xf8, // Time Stamp Register
CANSTMH: 0xf8, // Time Stamp Register
CANMSG: 0xfa, // Message Data Register
}
)
// Bitfields for FUSE: Fuses
const (
// EXTENDED
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
EXTENDED_TA0SEL = 0x1 // Reserved for factory tests
// HIGH
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
HIGH_WDTON = 0x10 // Watchdog timer always on
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
HIGH_BOOTSZ = 0x6 // Select Boot Size
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
// LOW
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally; [CKDIV8=0]
LOW_CKOUT = 0x40 // Clock output on PORTC7; [CKOUT=0]
LOW_SUT_CKSEL = 0x3f // Select Clock Source
)
// Bitfields for LOCKBIT: Lockbits
const (
// LOCKBIT
LOCKBIT_LB = 0x3 // Memory Lock
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
)
// Bitfields for SPI: Serial Peripheral Interface
const (
// SPCR: SPI Control Register
SPCR_SPIE = 0x80 // SPI Interrupt Enable
SPCR_SPE = 0x40 // SPI Enable
SPCR_DORD = 0x20 // Data Order
SPCR_MSTR = 0x10 // Master/Slave Select
SPCR_CPOL = 0x8 // Clock polarity
SPCR_CPHA = 0x4 // Clock Phase
SPCR_SPR = 0x3 // SPI Clock Rate Selects
// SPSR: SPI Status Register
SPSR_SPIF = 0x80 // SPI Interrupt Flag
SPSR_WCOL = 0x40 // Write Collision Flag
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
// SPDR: SPI Data Register
SPDR_SPD = 0xff // SPI Data Register
)
// Bitfields for TWI: Two Wire Serial Interface
const (
// TWCR: TWI Control Register
TWCR_TWINT = 0x80 // TWI Interrupt Flag
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
TWCR_TWWC = 0x8 // TWI Write Collition Flag
TWCR_TWEN = 0x4 // TWI Enable Bit
TWCR_TWIE = 0x1 // TWI Interrupt Enable
// TWSR: TWI Status Register
TWSR_TWS = 0xf8 // TWI Status
TWSR_TWPS = 0x3 // TWI Prescaler
// TWAR: TWI (Slave) Address register
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
)
// Bitfields for USART: USART
const (
// UCSR0A: USART Control and Status Register A
UCSR0A_RXC0 = 0x80 // USART Receive Complete
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
UCSR0A_FE0 = 0x10 // Framing Error
UCSR0A_DOR0 = 0x8 // Data overRun
UCSR0A_UPE0 = 0x4 // Parity Error
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
// UCSR0B: USART Control and Status Register B
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
UCSR0B_RXEN0 = 0x10 // Receiver Enable
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
UCSR0B_UCSZ02 = 0x4 // Character Size
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
// UCSR0C: USART Control and Status Register C
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
UCSR0C_USBS0 = 0x8 // Stop Bit Select
UCSR0C_UCSZ0 = 0x6 // Character Size
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
// UCSR1A: USART Control and Status Register A
UCSR1A_RXC1 = 0x80 // USART Receive Complete
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
UCSR1A_FE1 = 0x10 // Framing Error
UCSR1A_DOR1 = 0x8 // Data overRun
UCSR1A_UPE1 = 0x4 // Parity Error
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
// UCSR1B: USART Control and Status Register B
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
UCSR1B_RXEN1 = 0x10 // Receiver Enable
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
UCSR1B_UCSZ12 = 0x4 // Character Size
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
// UCSR1C: USART Control and Status Register C
UCSR1C_UMSEL1 = 0x40 // USART Mode Select
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
UCSR1C_USBS1 = 0x8 // Stop Bit Select
UCSR1C_UCSZ1 = 0x6 // Character Size
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
)
// Bitfields for CPU: CPU Registers
const (
// SREG: Status Register
SREG_I = 0x80 // Global Interrupt Enable
SREG_T = 0x40 // Bit Copy Storage
SREG_H = 0x20 // Half Carry Flag
SREG_S = 0x10 // Sign Bit
SREG_V = 0x8 // Two's Complement Overflow Flag
SREG_N = 0x4 // Negative Flag
SREG_Z = 0x2 // Zero Flag
SREG_C = 0x1 // Carry Flag
// XMCRA: External Memory Control Register A
XMCRA_SRE = 0x80 // External SRAM Enable
XMCRA_SRL = 0x70 // Wait state page limit
XMCRA_SRW1 = 0xc // Wait state select bit upper page
XMCRA_SRW0 = 0x3 // Wait state select bit lower page
// XMCRB: External Memory Control Register B
XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable
XMCRB_XMM = 0x7 // External Memory High Mask
// OSCCAL: Oscillator Calibration Value
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
// CLKPR: Clock Prescale Register
CLKPR_CLKPCE = 0x80
CLKPR_CLKPS = 0xf
// SMCR: Sleep Mode Control Register
SMCR_SM = 0xe // Sleep Mode Select bits
SMCR_SE = 0x1 // Sleep Enable
// RAMPZ: RAM Page Z Select Register
RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0
// GPIOR2: General Purpose IO Register 2
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
// GPIOR1: General Purpose IO Register 1
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
// GPIOR0: General Purpose IO Register 0
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
)
// Bitfields for BOOT_LOAD: Bootloader
const (
// SPMCSR: Store Program Memory Control Register
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
SPMCSR_PGWRT = 0x4 // Page Write
SPMCSR_PGERS = 0x2 // Page Erase
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
)
// Bitfields for EXINT: External Interrupts
const (
// EICRA: External Interrupt Control Register A
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
// EICRB: External Interrupt Control Register B
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
// EIMSK: External Interrupt Mask Register
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
// EIFR: External Interrupt Flag Register
EIFR_INTF = 0xff // External Interrupt Flags
)
// Bitfields for EEPROM: EEPROM
const (
// EEARL: EEPROM Read/Write Access Bytes
// EEARH: EEPROM Read/Write Access Bytes
EEAR_EEAR = 0xfff // EEPROM Address bits
// EEDR: EEPROM Data Register
EEDR_EEDR = 0xff // EEPROM Data bits
// EECR: EEPROM Control Register
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
EECR_EEWE = 0x2 // EEPROM Write Enable
EECR_EERE = 0x1 // EEPROM Read Enable
)
// Bitfields for TC8: Timer/Counter, 8-bit
const (
// TCCR0A: Timer/Counter0 Control Register
TCCR0A_FOC0A = 0x80 // Force Output Compare
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
TCCR0A_CS0 = 0x7 // Clock Selects
// OCR0A: Timer/Counter0 Output Compare Register
OCR0A_OCR0A = 0xff // Output Compare A bits
// TIMSK0: Timer/Counter0 Interrupt Mask Register
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
// TIFR0: Timer/Counter0 Interrupt Flag register
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
)
// Bitfields for TC16: Timer/Counter, 16-bit
const (
// TCCR1A: Timer/Counter1 Control Register A
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
// TCCR1B: Timer/Counter1 Control Register B
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
// TCCR1C: Timer/Counter 1 Control Register C
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
TCCR1C_FOC1C = 0x20 // Force Output Compare 1C
// TIMSK1: Timer/Counter Interrupt Mask Register
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output CompareC Match Interrupt Enable
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
// TIFR1: Timer/Counter Interrupt Flag register
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
TIFR1_OCF1C = 0x8 // Output Compare Flag 1C
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
// TCCR3A: Timer/Counter3 Control Register A
TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits
TCCR3A_WGM3 = 0x3 // Waveform Generation Mode
// TCCR3B: Timer/Counter3 Control Register B
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode
TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3
// TCCR3C: Timer/Counter 3 Control Register C
TCCR3C_FOC3A = 0x80 // Force Output Compare 3A
TCCR3C_FOC3B = 0x40 // Force Output Compare 3B
TCCR3C_FOC3C = 0x20 // Force Output Compare 3C
// TIMSK3: Timer/Counter Interrupt Mask Register
TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output CompareC Match Interrupt Enable
TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output CompareB Match Interrupt Enable
TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output CompareA Match Interrupt Enable
TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable
// TIFR3: Timer/Counter Interrupt Flag register
TIFR3_ICF3 = 0x20 // Input Capture Flag 3
TIFR3_OCF3C = 0x8 // Output Compare Flag 3C
TIFR3_OCF3B = 0x4 // Output Compare Flag 3B
TIFR3_OCF3A = 0x2 // Output Compare Flag 3A
TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag
)
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
const (
// TCCR2A: Timer/Counter2 Control Register
TCCR2A_FOC2A = 0x80 // Force Output Compare
TCCR2A_WGM20 = 0x40 // Waveform Genration Mode
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
TCCR2A_CS2 = 0x7 // Clock Select bits
// TIMSK2: Timer/Counter Interrupt Mask register
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
// TIFR2: Timer/Counter Interrupt Flag Register
TIFR2_OCF2A = 0x2 // Output Compare Flag 2
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
// ASSR: Asynchronous Status Register
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
)
// Bitfields for WDT: Watchdog Timer
const (
// WDTCR: Watchdog Timer Control Register
WDTCR_WDCE = 0x10 // Watchdog Change Enable
WDTCR_WDE = 0x8 // Watch Dog Enable
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
)
// Bitfields for ADC: Analog-to-Digital Converter
const (
// ADMUX: The ADC multiplexer Selection Register
ADMUX_REFS = 0xc0 // Reference Selection Bits
ADMUX_ADLAR = 0x20 // Left Adjust Result
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
// ADCSRA: The ADC Control and Status register
ADCSRA_ADEN = 0x80 // ADC Enable
ADCSRA_ADSC = 0x40 // ADC Start Conversion
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
// DIDR0: Digital Input Disable Register 1
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
)
// Bitfields for AC: Analog Comparator
const (
// ACSR: Analog Comparator Control And Status Register
ACSR_ACD = 0x80 // Analog Comparator Disable
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
ACSR_ACO = 0x20 // Analog Compare Output
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
// DIDR1
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
)
// Bitfields for CAN: Controller Area Network
const (
// CANGCON: CAN General Control Register
CANGCON_ABRQ = 0x80 // Abort Request
CANGCON_OVRQ = 0x40 // Overload Frame Request
CANGCON_TTC = 0x20 // Time Trigger Communication
CANGCON_SYNTTC = 0x10 // Synchronization of TTC
CANGCON_LISTEN = 0x8 // Listening Mode
CANGCON_TEST = 0x4 // Test Mode
CANGCON_ENASTB = 0x2 // Enable / Standby
CANGCON_SWRES = 0x1 // Software Reset Request
// CANGSTA: CAN General Status Register
CANGSTA_OVRG = 0x40 // Overload Frame Flag
CANGSTA_TXBSY = 0x10 // Transmitter Busy
CANGSTA_RXBSY = 0x8 // Receiver Busy
CANGSTA_ENFG = 0x4 // Enable Flag
CANGSTA_BOFF = 0x2 // Bus Off Mode
CANGSTA_ERRP = 0x1 // Error Passive Mode
// CANGIT: CAN General Interrupt Register
CANGIT_CANIT = 0x80 // General Interrupt Flag
CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag
CANGIT_OVRTIM = 0x20 // Overrun CAN Timer
CANGIT_BXOK = 0x10 // Burst Receive Interrupt
CANGIT_SERG = 0x8 // Stuff Error General
CANGIT_CERG = 0x4 // CRC Error General
CANGIT_FERG = 0x2 // Form Error General
CANGIT_AERG = 0x1 // Ackknowledgement Error General
// CANGIE: CAN General Interrupt Enable Register
CANGIE_ENIT = 0x80 // Enable all Interrupts
CANGIE_ENBOFF = 0x40 // Enable Bus Off INterrupt
CANGIE_ENRX = 0x20 // Enable Receive Interrupt
CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt
CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt
CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt
CANGIE_ENERG = 0x2 // Enable General Error Interrupt
CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt
// CANEN2: Enable MOb Register
CANEN2_ENMOB = 0xff // Enable MOb
// CANEN1: Enable MOb Register
CANEN1_ENMOB = 0x7f // Enable MOb
// CANIE2: Enable Interrupt MOb Register
CANIE2_IEMOB = 0xff // Interrupt Enable by MOb
// CANIE1: Enable Interrupt MOb Register
CANIE1_IEMOB = 0x7f // Interrupt Enable by MOb
// CANSIT2: CAN Status Interrupt MOb Register
CANSIT2_SIT = 0xff // Status of Interrupt by MOb
// CANSIT1: CAN Status Interrupt MOb Register
CANSIT1_SIT = 0x7f // Status of Interrupt by MOb
// CANBT1: Bit Timing Register 1
CANBT1_BRP = 0x7e // Baud Rate Prescaler bits
// CANBT2: Bit Timing Register 2
CANBT2_SJW = 0x60 // Re-Sync Jump Width
CANBT2_PRS = 0xe // Propagation Time Segment
// CANBT3: Bit Timing Register 3
CANBT3_PHS2 = 0x70 // Phase Segments
CANBT3_PHS1 = 0xe // Phase Segment 1
CANBT3_SMP = 0x1 // Sample Type
// CANTCON: Timer Control Register
CANTCON_TPRSC = 0xff // CAN Timer Prescaler
// CANTIML: Timer Register
// CANTIMH: Timer Register
CANTIM_CANTIM = 0xffff // CAN Timer Count
// CANTTCL: TTC Timer Register
// CANTTCH: TTC Timer Register
CANTTC_TIMTTC = 0xffff // TTC Timer Count
// CANTEC: Transmit Error Counter Register
CANTEC_TEC = 0xff // Trasnmit Error Count
// CANREC: Receive Error Counter Register
CANREC_REC = 0xff // Receive Error Count
// CANHPMOB: Highest Priority MOb Register
CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb number
CANHPMOB_CGP = 0xf // CAN General purpose bits
// CANPAGE: Page MOb Register
CANPAGE_MOBNB = 0xf0 // MOb Number Bits
CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment
CANPAGE_INDX = 0x7 // Data Buffer Index Bits
// CANSTMOB: MOb Status Register
CANSTMOB_DLCW = 0x80 // Data Length Code Warning
CANSTMOB_TXOK = 0x40 // Transmit OK
CANSTMOB_RXOK = 0x20 // Receive OK
CANSTMOB_BERR = 0x10 // Bit Error
CANSTMOB_SERR = 0x8 // Stuff Error
CANSTMOB_CERR = 0x4 // CRC Error
CANSTMOB_FERR = 0x2 // Form Error
CANSTMOB_AERR = 0x1 // Ackknowledgement Error
// CANCDMOB: MOb Control and DLC Register
CANCDMOB_CONMOB = 0xc0 // MOb Config Bits
CANCDMOB_RPLV = 0x20 // Reply Valid
CANCDMOB_IDE = 0x10 // Identifier Extension
CANCDMOB_DLC = 0xf // Data Length Code Bits
// CANIDT4: Identifier Tag Register 4
CANIDT4_IDT = 0xf8 // Identifier Tag
CANIDT4_RTRTAG = 0x4 // Remote Trasnmission Request Tag
CANIDT4_RB1TAG = 0x2 // Reserved Bit 1 Tag
CANIDT4_RB0TAG = 0x1 // Reserved Bit 0 Tag
// CANIDT3: Identifier Tag Register 3
CANIDT3_IDT = 0xff // Identifier Tag
// CANIDT2: Identifier Tag Register 2
CANIDT2_IDT = 0xff // Identifier Tag
// CANIDT1: Identifier Tag Register 1
CANIDT1_IDT = 0xff // Identifier Tag
// CANIDM4: Identifier Mask Register 4
CANIDM4_IDMSK = 0xf8 // Identifier Mask
CANIDM4_RTRMSK = 0x4 // Remote Transmission Request Mask
CANIDM4_IDEMSK = 0x1 // Identifier Extension Mask
// CANIDM3: Identifier Mask Register 3
CANIDM3_IDMSK = 0xff // Identifier Mask
// CANIDM2: Identifier Mask Register 2
CANIDM2_IDMSK = 0xff // Identifier Mask
// CANIDM1: Identifier Mask Register 1
CANIDM1_IDMSK = 0xff // Identifier Mask
// CANSTML: Time Stamp Register
// CANSTMH: Time Stamp Register
CANSTM_TIMSTM = 0xffff // Time Stamp Count
// CANMSG: Message Data Register
CANMSG_MSG = 0xff // Message Data
)
Reference in New Issue View Git Blame Copy Permalink