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https://github.com/tinygo-org/tinygo.git
synced 2026-08-06 03:53:42 +00:00
Ayke van Laethem
8cd2a462b9
There is no reason to specialize this per chip as it is only ever used for JavaScript. Not only that, it is causing confusion and is yet another quirk to learn when porting the runtime to a new microcontroller.
80 lines
2.2 KiB
Go
80 lines
2.2 KiB
Go
// +build stm32,stm32f103
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package runtime
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import (
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"device/stm32"
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"machine"
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)
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/*
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timer settings used for tick and sleep.
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note: TICK_TIMER_FREQ and SLEEP_TIMER_FREQ are controlled by PLL / clock
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settings configured in initCLK, so must be kept in sync if the clock settings
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are changed.
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*/
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const (
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TICK_RATE = 1000 // 1 KHz
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SLEEP_TIMER_IRQ = stm32.IRQ_TIM3
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SLEEP_TIMER_FREQ = 72000000 // 72 MHz
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TICK_TIMER_IRQ = stm32.IRQ_TIM4
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TICK_TIMER_FREQ = 72000000 // 72 MHz
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)
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type arrtype = uint32
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func init() {
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initCLK()
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initSleepTimer(&timerInfo{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM3EN,
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Device: stm32.TIM3,
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})
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machine.UART0.Configure(machine.UARTConfig{})
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initTickTimer(&timerInfo{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM4EN,
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Device: stm32.TIM4,
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})
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}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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// initCLK sets clock to 72MHz using HSE 8MHz crystal w/ PLL X 9 (8MHz x 9 = 72MHz).
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func initCLK() {
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stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2) // Two wait states, per datasheet
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON) // enable HSE clock
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// wait for the HSEREADY flag
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
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}
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION) // enable HSI clock
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// wait for the HSIREADY flag
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) {
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}
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PLLSRC) // set PLL source to HSE
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PLLMUL_Mul9 << stm32.RCC_CFGR_PLLMUL_Pos) // multiply by 9
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON) // enable the PLL
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// wait for the PLLRDY flag
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_SW_PLL) // set clock source to pll
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// wait for PLL to be CLK
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for !stm32.RCC.CFGR.HasBits(stm32.RCC_CFGR_SWS_PLL << stm32.RCC_CFGR_SWS_Pos) {
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}
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}
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