mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-03 18:47:47 +00:00
Ayke van Laethem
98f84a497d
There were a few issues that were causing qemu-system-arm and
qemu-system-riscv to give the wrong exit codes. They are in fact capable
of exiting with 0 or 1 signalled from the running application, but this
functionality wasn't used. This commit changes this in the following
ways:
* It fixes SemiHosting codes, which were incorrectly written in
decimal while they should have been written in hexadecimal (oops!).
* It modifies all the baremetal main functions (aka reset handlers) to
exit with `exit(0)` instead of `abort()`.
* It changes `syscall.Exit` to call `exit(code)` instead of `abort()`
on baremetal targets.
* It adds these new exit functions where necessary, implemented in a
way that signals the correct exit status if running under QEMU.
All in all, this means that `tinygo test` doesn't have to look at the
output of a test to determine the outcome. It can simply look at the
exit code.
68 lines
2.0 KiB
Go
68 lines
2.0 KiB
Go
// +build esp32
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package runtime
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import (
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"device"
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"device/esp"
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"machine"
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)
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// This is the function called on startup right after the stack pointer has been
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// set.
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//export main
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func main() {
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// Disable both watchdog timers that are enabled by default on startup.
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// Note that these watchdogs can be protected, but the ROM bootloader
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// doesn't seem to protect them.
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esp.RTCCNTL.WDTCONFIG0.Set(0)
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esp.TIMG0.WDTCONFIG0.Set(0)
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// Switch SoC clock source to PLL (instead of the default which is XTAL).
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// This switches the CPU (and APB) clock from 40MHz to 80MHz.
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// Options:
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// RTCCNTL_CLK_CONF_SOC_CLK_SEL: PLL (default XTAL)
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// RTCCNTL_CLK_CONF_CK8M_DIV_SEL: 2 (default)
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// RTCCNTL_CLK_CONF_DIG_CLK8M_D256_EN: Enable (default)
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// RTCCNTL_CLK_CONF_CK8M_DIV: DIV256 (default)
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// The only real change made here is modifying RTCCNTL_CLK_CONF_SOC_CLK_SEL,
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// but setting a fixed value produces smaller code.
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esp.RTCCNTL.CLK_CONF.Set((esp.RTCCNTL_CLK_CONF_SOC_CLK_SEL_PLL << esp.RTCCNTL_CLK_CONF_SOC_CLK_SEL_Pos) |
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(2 << esp.RTCCNTL_CLK_CONF_CK8M_DIV_SEL_Pos) |
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(esp.RTCCNTL_CLK_CONF_DIG_CLK8M_D256_EN_Enable << esp.RTCCNTL_CLK_CONF_DIG_CLK8M_D256_EN_Pos) |
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(esp.RTCCNTL_CLK_CONF_CK8M_DIV_DIV256 << esp.RTCCNTL_CLK_CONF_CK8M_DIV_Pos))
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// Switch CPU from 80MHz to 160MHz. This doesn't affect the APB clock,
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// which is still running at 80MHz.
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esp.DPORT.CPU_PER_CONF.Set(esp.DPORT_CPU_PER_CONF_CPUPERIOD_SEL_SEL_160)
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// Clear .bss section. .data has already been loaded by the ROM bootloader.
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// Do this after increasing the CPU clock to possibly make startup slightly
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// faster.
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clearbss()
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// Initialize UART.
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machine.Serial.Configure(machine.UARTConfig{})
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// Initialize main system timer used for time.Now.
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initTimer()
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// Initialize the heap, call main.main, etc.
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run()
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// Fallback: if main ever returns, hang the CPU.
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exit(0)
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}
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//go:extern _sbss
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var _sbss [0]byte
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//go:extern _ebss
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var _ebss [0]byte
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func abort() {
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for {
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device.Asm("waiti 0")
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}
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}
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