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ardnew
131 lines
3.6 KiB
Go
131 lines
3.6 KiB
Go
// +build mimxrt1062
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package usb2
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// Implementation of USB host controller driver (hcd) for NXP iMXRT1062.
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import (
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"device/arm"
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"device/nxp"
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"runtime/interrupt"
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"runtime/volatile"
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)
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// hcdCount defines the number of USB cores to configure for host mode. It is
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// computed as the sum of all declared host configuration descriptors.
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const hcdCount = 0
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// hcdInterruptPriority defines the priority for all USB host interrupts.
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const hcdInterruptPriority = 3
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// hostController implements USB host controller driver (hcd) interface.
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type hostController struct {
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core *core // Parent USB core this instance is attached to
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port int // USB port index
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cc class // USB host class
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id int // hostControllerInstance index
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bus *nxp.USB_Type
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phy *nxp.USBPHY_Type
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irq interrupt.Interrupt
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cri volatile.Register8 // set to 1 if in critical section, else 0
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ivm uintptr // interrupt state when entering critical section
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}
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// hostControllerInstance provides statically-allocated instances of each USB
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// host controller configured on this platform.
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var hostControllerInstance [hcdCount]hostController
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// initHCD initializes and assigns a free host controller instance to the given
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// USB port. Returns the initialized host controller or nil if no free host
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// controller instances remain.
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func initHCD(port int, class class) (hcd, status) {
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if 0 == hcdCount {
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return nil, statusInvalid // must have defined host controllers
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}
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// Return the first instance whose assigned core is currently nil.
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for i := range hostControllerInstance {
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if nil == hostControllerInstance[i].core {
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// Initialize host controller.
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hostControllerInstance[i].core = &coreInstance[port]
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hostControllerInstance[i].port = port
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hostControllerInstance[i].cc = class
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hostControllerInstance[i].id = i
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switch port {
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case 0:
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hostControllerInstance[i].bus = nxp.USB1
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hostControllerInstance[i].phy = nxp.USBPHY1
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hostControllerInstance[i].irq =
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interrupt.New(nxp.IRQ_USB_OTG1,
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func(interrupt.Interrupt) {
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coreInstance[0].hc.interrupt()
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})
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case 1:
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hostControllerInstance[i].bus = nxp.USB2
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hostControllerInstance[i].phy = nxp.USBPHY2
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hostControllerInstance[i].irq =
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interrupt.New(nxp.IRQ_USB_OTG2,
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func(interrupt.Interrupt) {
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//coreInstance[1].hc.interrupt()
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})
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}
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return &hostControllerInstance[i], statusOK
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}
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}
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return nil, statusBusy // No free host controller instances available.
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}
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func (hc *hostController) class() class { return hc.cc }
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func (hc *hostController) init() status {
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return statusOK
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}
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func (hc *hostController) enable(enable bool) status {
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hc.irq.SetPriority(hcdInterruptPriority)
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hc.irq.Enable()
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return statusOK
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}
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func (hc *hostController) critical(enter bool) status {
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if enter {
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// check if critical section already locked
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if hc.cri.Get() != 0 {
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return statusRetry
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}
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// lock critical section
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hc.cri.Set(1)
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// disable interrupts, storing state in receiver
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hc.ivm = arm.DisableInterrupts()
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} else {
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// ensure critical section is locked
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if hc.cri.Get() != 0 {
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// re-enable interrupts, using state stored in receiver
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arm.EnableInterrupts(hc.ivm)
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// unlock critical section
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hc.cri.Set(0)
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}
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}
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return statusOK
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}
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func (hc *hostController) interrupt() {
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}
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// udelay waits for the given number of microseconds before returning.
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// We cannot use the sleep timer from this context (import cycle), but we need
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// an approximate method to spin CPU cycles for short periods of time.
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//go:inline
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func (hc *hostController) udelay(microsec uint32) {
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n := cycles(microsec, descCPUFrequencyHz)
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for i := uint32(0); i < n; i++ {
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arm.Asm(`nop`)
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}
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}
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