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https://github.com/tinygo-org/tinygo.git
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Konstantin Sharlaimov
c1a4ed1489
STM32F4 and F7 share the same OTG FS IP but have no USB driver in TinyGo. This adds a full device-mode driver covering CDC, HID, and MSC with working examples. - OTG FS has 4 physical EPs (0–3); virtual indices 4–7 fold onto them via physEP() so the existing machine/usb API is unchanged - F4 bypasses VBUS sensing via GCCFG.NOVBUSSENS; F7 uses the USB voltage regulator + GOTGCTL B-valid override instead - STM32F7 PLL_Q changed 2→9 to produce the 48 MHz clock required by USB/RNG/SDMMC; CK48MSEL cleared to select main PLL as source - HID and MSC descriptors remapped at init() to physical endpoint addresses (EP2/EP1 for HID, EP2/EP3 for MSC) - usb-storage example replaced machine.Flash with a FAT12 RAM disk so the host mounts without reformatting - MSC sendCSW sets queuedBytes before state transition to fix a missed byte-count on the status phase
35 lines
1.0 KiB
Go
35 lines
1.0 KiB
Go
//go:build stm32f7
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package machine
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import (
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"device/arm"
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"device/stm32"
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)
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// initOTGFSPHY enables the STM32F7 OTG FS PHY and overrides B-session VBUS
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// detection via GOTGCTL so boards without VBUS sensing still enumerate.
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func initOTGFSPHY() {
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// Enable USB voltage regulator (specific to F72x/F73x).
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// Bit 14 in PWR_CR2 is USBREGEN.
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stm32.PWR.CR2.SetBits(1 << 14)
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// Stabilization delay for the regulator (~100us is plenty).
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for i := 0; i < 10000; i++ {
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arm.Asm("nop")
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}
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// Enable FS PHY.
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stm32.OTG_FS_GLOBAL.GCCFG.SetBits(stm32.USB_OTG_FS_GCCFG_PWRDWN)
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// Disable hardware VBUS detection (F7 uses VBDEN, opposite polarity to F4's NOVBUSSENS).
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// Clearing this prevents the peripheral from gating enumeration on PA9 VBUS level.
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stm32.OTG_FS_GLOBAL.GCCFG.ClearBits(stm32.USB_OTG_FS_GCCFG_VBDEN)
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// Override B-session valid so GOTGCTL-based detection reports device connected.
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stm32.OTG_FS_GLOBAL.GOTGCTL.SetBits(
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stm32.USB_OTG_FS_GOTGCTL_BVALOEN | // enable B-valid override
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stm32.USB_OTG_FS_GOTGCTL_BVALOVAL, // set B-valid = 1
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)
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}
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