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Konstantin Sharlaimov
5f02d6b659
Define the board's external crystal (HSE) frequency `xtalHz` in the respective `board_*.go` files. Per-topology PLL tables (F1, F4, F7) will compute the register dividers from it. Moving this parameter to the board definition level cleanly isolates board hardware characteristics from general MCU chip configurations, eliminating the need for custom target build tags. Targets using HSE-clocked STM32 chips must define `xtalHz` or fail to build.
21 lines
660 B
Go
21 lines
660 B
Go
//go:build stm32f4 && (stm32f405 || stm32f407)
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package machine
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// PLLParams168MHz returns the HSE PLL dividers needed to reach a 336MHz VCO
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// (168MHz SYSCLK, P=2, Q=7) for the configured crystal frequency. M is chosen
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// to bring the PLL input (HSE/M) to 2MHz, the value RM0090 pg. 95 recommends
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// to minimize jitter; the previous hardcoded F407 table used 1MHz.
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func PLLParams168MHz() PLLParams {
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switch xtalHz {
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case 8_000_000:
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return PLLParams{M: 4, N: 168, P: 2, Q: 7}
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case 12_000_000:
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return PLLParams{M: 6, N: 168, P: 2, Q: 7}
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case 16_000_000:
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return PLLParams{M: 8, N: 168, P: 2, Q: 7}
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default:
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panic("unsupported xtal frequency")
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}
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}
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