mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-05 11:37:46 +00:00
deadprogram
4c3680635e
The UART handleInterrupt handler unconditionally read RDR on every interrupt without checking which flag triggered it. On newer STM32 USART peripherals (U5, L4, L5, L0, G0, F7, WL), RXNEIE enables interrupts for both RXFNE (data ready) and ORE (overrun error). Unlike older families (F1, F4), ORE is not cleared by reading the data register, it must be explicitly cleared via the ICR register. When an overrun occurred (e.g. serial data arriving while ADC busy-waits in Get()), ORE would trigger the interrupt, the handler would fire without clearing it, and the interrupt would re-trigger immediately, causing an infinite interrupt storm that locks up the CPU. Fix by: - Checking RXFNE/RXNE (bit 5) before reading data from RDR - Clearing ORE (bit 3) via ICR on newer peripherals when set - Adding errClearReg field to UART struct, set to &Bus.ICR in setRegisters() for all ICR-capable families - Preserving the SR+DR clearing sequence for older F1/F4 families Signed-off-by: deadprogram <ron@hybridgroup.com>
556 lines
15 KiB
Go
556 lines
15 KiB
Go
//go:build stm32wlx
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package machine
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// Peripheral abstraction layer for the stm32wle5
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import (
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"device/stm32"
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"errors"
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"internal/binary"
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"math/bits"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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var deviceIDAddr = []uintptr{0x1FFF7590, 0x1FFF7594, 0x1FFF7598}
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const (
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AF0_SYSTEM = 0
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AF1_TIM1_2_LPTIM1 = 1
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AF2_TIM1_2 = 2
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AF3_SPIS2_TIM1_LPTIM3 = 3
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AF4_I2C1_2_3 = 4
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AF5_SPI1_SPI2S2 = 5
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AF6_RF = 6
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AF7_USART1_2 = 7
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AF8_LPUART1 = 8
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AF12_COMP1_2_TIM1 = 12
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AF13_DEBUG = 13
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AF14_TIM2_16_17_LPTIM2 = 14
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AF15_EVENTOUT = 15
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)
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const (
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SYSCLK = 48e6
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APB1_TIM_FREQ = SYSCLK
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APB2_TIM_FREQ = SYSCLK
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)
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func CPUFrequency() uint32 {
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return SYSCLK
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}
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PH3 = portH + 3
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 7:
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return stm32.GPIOH
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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switch p / 16 {
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case 0:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN)
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case 1:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN)
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case 2:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN)
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case 7:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOHEN)
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default:
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panic("machine: unknown port")
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}
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}
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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// APB1ENR1
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case unsafe.Pointer(stm32.LPTIM1): // LPTIM1 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_LPTIM1EN)
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case unsafe.Pointer(stm32.DAC): // DAC clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_DAC1EN)
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case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN)
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case unsafe.Pointer(stm32.SPI2): // SPI2S2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2S2EN)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN)
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// APB1ENR2
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case unsafe.Pointer(stm32.LPTIM3): // LPTIM3 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM3EN)
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case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN)
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case unsafe.Pointer(stm32.LPUART): // LPUART clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN)
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//APB2ENR
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case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM17EN)
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case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
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case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
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case unsafe.Pointer(stm32.ADC): // ADC clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADCEN)
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}
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}
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func handlePinInterrupt(pin uint8) {
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if stm32.EXTI.PR1.HasBits(1 << pin) {
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// Writing 1 to the pending register clears the
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// pending flag for that bit
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stm32.EXTI.PR1.Set(1 << pin)
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callback := pinCallbacks[pin]
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if callback != nil {
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callback(interruptPins[pin])
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}
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}
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}
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func (p Pin) registerInterrupt() interrupt.Interrupt {
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pin := uint8(p) % 16
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switch pin {
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case 0:
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return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) })
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case 1:
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return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) })
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case 2:
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return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) })
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case 3:
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return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) })
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case 4:
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return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) })
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case 5:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) })
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case 6:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) })
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case 7:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) })
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case 8:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) })
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case 9:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) })
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case 10:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) })
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case 11:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) })
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case 12:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) })
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case 13:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) })
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case 14:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) })
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case 15:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) })
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}
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return interrupt.Interrupt{}
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}
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// -- SPI ----------------------------------------------------------------------
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type SPI struct {
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Bus *stm32.SPI_Type
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AltFuncSelector uint8
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}
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func (spi *SPI) config8Bits() {
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// Set rx threshold to 8-bits, so RXNE flag is set for 1 byte
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// (common STM32 SPI implementation does 8-bit transfers only)
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spi.Bus.CR2.SetBits(stm32.SPI_CR2_FRXTH)
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}
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func (spi *SPI) configurePins(config SPIConfig) {
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config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector)
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config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector)
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config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector)
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}
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func (spi *SPI) getBaudRate(config SPIConfig) uint32 {
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var clock uint32
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// We keep this switch and separate management of SPI Clocks
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// for future improvement of system/bus clocks and prescalers
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switch spi.Bus {
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case stm32.SPI1:
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clock = CPUFrequency()
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case stm32.SPI2, stm32.SPI3:
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clock = CPUFrequency()
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}
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// limit requested frequency to bus frequency and min frequency (DIV256)
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freq := config.Frequency
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if min := clock / 256; freq < min {
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freq = min
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} else if freq > clock {
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freq = clock
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}
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// calculate the exact clock divisor (freq=clock/div -> div=clock/freq).
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// truncation is fine, since it produces a less-than-or-equal divisor, and
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// thus a greater-than-or-equal frequency.
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// divisors only come in consecutive powers of 2, so we can use log2 (or,
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// equivalently, bits.Len - 1) to convert to respective enum value.
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div := bits.Len32(clock/freq) - 1
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// but DIV1 (2^0) is not permitted, as the least divisor is DIV2 (2^1), so
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// subtract 1 from the log2 value, keeping a lower bound of 0
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if div < 0 {
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div = 0
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} else if div > 0 {
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div--
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}
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// finally, shift the enumerated value into position for SPI CR1
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return uint32(div) << stm32.SPI_CR1_BR_Pos
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}
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//---------- I2C related code
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// Gets the value for TIMINGR register
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func (i2c *I2C) getFreqRange(br uint32) uint32 {
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// This is a 'magic' value calculated by STM32CubeMX
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// for 48Mhz PCLK1.
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// TODO: Do calculations based on PCLK1
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switch br {
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case 10 * KHz:
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return 0x9010DEFF
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case 100 * KHz:
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return 0x20303E5D
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case 400 * KHz:
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return 0x2010091A
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case 500 * KHz:
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return 0x00201441
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default:
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return 0
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}
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}
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//---------- UART related code
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// Configure the UART.
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func (uart UART) configurePins(config UARTConfig) {
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// enable the alternate functions on the TX and RX pins
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config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector)
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config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector)
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}
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// UART baudrate calc based on the bus and clockspeed
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// NOTE: keep this in sync with the runtime/runtime_stm32wle5.go clock init code
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func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
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var br uint32
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uartClock := CPUFrequency() // No Prescaler configuration
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br = uint32((uartClock + baudRate/2) / baudRate)
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return (br)
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}
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// Register names vary by ST processor, these are for STM L5
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func (uart *UART) setRegisters() {
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uart.rxReg = &uart.Bus.RDR
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uart.txReg = &uart.Bus.TDR
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uart.statusReg = &uart.Bus.ISR
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uart.txEmptyFlag = stm32.USART_ISR_TXFNF //(TXFNF == TXE == bit 7, but depends alternate RM0461/1094)
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uart.errClearReg = &uart.Bus.ICR
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}
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//---------- Timer related code
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var (
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TIM1 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM1EN,
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Device: stm32.TIM1,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA8, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA9, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA10, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA11, AF1_TIM1_2_LPTIM1}}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM2EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA0, AF1_TIM1_2_LPTIM1}, {PA5, AF1_TIM1_2_LPTIM1}, {PA15, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA1, AF1_TIM1_2_LPTIM1}, {PB3, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA2, AF1_TIM1_2_LPTIM1}, {PB10, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA3, AF1_TIM1_2_LPTIM1}, {PB11, AF1_TIM1_2_LPTIM1}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM16 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM16EN,
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Device: stm32.TIM16,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA6, AF14_TIM2_16_17_LPTIM2}}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM17 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM17EN,
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Device: stm32.TIM17,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA7, AF1_TIM1_2_LPTIM1}, {PB9, AF1_TIM1_2_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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)
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func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
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switch t {
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case &TIM1:
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return interrupt.New(stm32.IRQ_TIM1_UP, TIM1.handleUPInterrupt)
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case &TIM2:
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return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
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case &TIM16:
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return interrupt.New(stm32.IRQ_TIM16, TIM16.handleUPInterrupt)
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case &TIM17:
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return interrupt.New(stm32.IRQ_TIM17, TIM17.handleUPInterrupt)
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}
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return interrupt.Interrupt{}
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}
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func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
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switch t {
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case &TIM1:
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return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt)
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case &TIM2:
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return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
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case &TIM16:
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return interrupt.New(stm32.IRQ_TIM16, TIM16.handleOCInterrupt)
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case &TIM17:
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return interrupt.New(stm32.IRQ_TIM17, TIM17.handleOCInterrupt)
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}
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return interrupt.Interrupt{}
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}
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func (t *TIM) enableMainOutput() {
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t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE)
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}
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func initRNG() {
|
|
stm32.RCC.AHB3ENR.SetBits(stm32.RCC_AHB3ENR_RNGEN)
|
|
|
|
// Enable RNG with config.A (See RM0453 22.6.2)
|
|
stm32.RNG.CR.Set(0x40F00D40) // RNG Config. A
|
|
stm32.RNG.HTCR.Set(0x17590ABC) // MAGIC NUMBER
|
|
stm32.RNG.HTCR.Set(0x0000AA74) // HTCR VALUE
|
|
stm32.RNG.CR.Set(0x00F00D4C) // CONFIG A + RNG_EN=1 + IE=1
|
|
}
|
|
|
|
//----------
|
|
|
|
type arrtype = uint32
|
|
type psctype = uint32
|
|
type arrRegType = volatile.Register32
|
|
|
|
const (
|
|
ARR_MAX = 0x10000
|
|
PSC_MAX = 0x10000
|
|
)
|
|
|
|
//---------- Flash related code
|
|
|
|
const eraseBlockSizeValue = 2048
|
|
|
|
// eraseBlock of the passed in block number
|
|
func eraseBlock(block uint32) error {
|
|
waitUntilFlashDone()
|
|
|
|
// check if operation is allowed.
|
|
if stm32.FLASH.GetSR_PESD() != 0 {
|
|
return errFlashCannotErasePage
|
|
}
|
|
|
|
// clear any previous errors
|
|
stm32.FLASH.SR.SetBits(0x3FA)
|
|
|
|
// page erase operation
|
|
stm32.FLASH.SetCR_PER(1)
|
|
defer stm32.FLASH.SetCR_PER(0)
|
|
|
|
// set the address to the page to be written
|
|
stm32.FLASH.SetCR_PNB(block)
|
|
defer stm32.FLASH.SetCR_PNB(0)
|
|
|
|
// start the page erase
|
|
stm32.FLASH.SetCR_STRT(1)
|
|
|
|
waitUntilFlashDone()
|
|
|
|
if err := checkError(); err != nil {
|
|
return err
|
|
}
|
|
|
|
return nil
|
|
}
|
|
|
|
const writeBlockSize = 8
|
|
|
|
func writeFlashData(address uintptr, data []byte) (int, error) {
|
|
if len(data)%writeBlockSize != 0 {
|
|
return 0, errFlashInvalidWriteLength
|
|
}
|
|
|
|
waitUntilFlashDone()
|
|
|
|
// check if operation is allowed
|
|
if stm32.FLASH.GetSR_PESD() != 0 {
|
|
return 0, errFlashNotAllowedWriteData
|
|
}
|
|
|
|
// clear any previous errors
|
|
stm32.FLASH.SR.SetBits(0x3FA)
|
|
|
|
for j := 0; j < len(data); j += writeBlockSize {
|
|
// start page write operation
|
|
stm32.FLASH.SetCR_PG(1)
|
|
|
|
// write first word using double-word high order word
|
|
*(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(data[j : j+writeBlockSize/2])
|
|
|
|
address += writeBlockSize / 2
|
|
|
|
// write second word using double-word low order word
|
|
*(*uint32)(unsafe.Pointer(address)) = binary.LittleEndian.Uint32(data[j+writeBlockSize/2 : j+writeBlockSize])
|
|
|
|
waitUntilFlashDone()
|
|
|
|
if err := checkError(); err != nil {
|
|
return j, err
|
|
}
|
|
|
|
// end flash write
|
|
stm32.FLASH.SetCR_PG(0)
|
|
address += writeBlockSize / 2
|
|
}
|
|
|
|
return len(data), nil
|
|
}
|
|
|
|
func waitUntilFlashDone() {
|
|
for stm32.FLASH.GetSR_BSY() != 0 {
|
|
}
|
|
|
|
for stm32.FLASH.GetSR_CFGBSY() != 0 {
|
|
}
|
|
}
|
|
|
|
var (
|
|
errFlashPGS = errors.New("errFlashPGS")
|
|
errFlashSIZE = errors.New("errFlashSIZE")
|
|
errFlashPGA = errors.New("errFlashPGA")
|
|
errFlashWRP = errors.New("errFlashWRP")
|
|
errFlashPROG = errors.New("errFlashPROG")
|
|
)
|
|
|
|
func checkError() error {
|
|
switch {
|
|
case stm32.FLASH.GetSR_PGSERR() != 0:
|
|
return errFlashPGS
|
|
case stm32.FLASH.GetSR_SIZERR() != 0:
|
|
return errFlashSIZE
|
|
case stm32.FLASH.GetSR_PGAERR() != 0:
|
|
return errFlashPGA
|
|
case stm32.FLASH.GetSR_WRPERR() != 0:
|
|
return errFlashWRP
|
|
case stm32.FLASH.GetSR_PROGERR() != 0:
|
|
return errFlashPROG
|
|
}
|
|
|
|
return nil
|
|
}
|