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deadprogram
2333ef2454
Add SPIv2 driver for STM32U5 using TXDR/RXDR and CFG1/CFG2 registers, which differ from the classic SPI peripheral on older STM32 families. Implements Configure() and single-byte Transfer(). Add SPI1 peripheral and pin definitions to arduino-uno-q board. Exclude stm32u5 from the shared classic SPI build tag.
120 lines
2.5 KiB
Go
120 lines
2.5 KiB
Go
//go:build stm32u5
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package machine
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// SPI on STM32U5 uses the new SPIv2 peripheral with separate TXDR/RXDR registers.
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import (
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"unsafe"
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)
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// SPIConfig is used to store config info for SPI.
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type SPIConfig struct {
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Frequency uint32
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SCK Pin
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SDO Pin
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SDI Pin
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LSBFirst bool
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Mode uint8
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}
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// Configure is intended to setup the STM32U5 SPI peripheral.
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func (spi *SPI) Configure(config SPIConfig) error {
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// Disable SPI interface before any configuration changes
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spi.Bus.CR1.ClearBits(1) // Clear SPE (bit 0)
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// Enable clock for SPI
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enableAltFuncClock(unsafe.Pointer(spi.Bus))
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// Init pins - use defaults if not specified
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if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 {
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config.SCK = SPI0_SCK_PIN
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config.SDO = SPI0_SDO_PIN
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config.SDI = SPI0_SDI_PIN
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}
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spi.configurePins(config)
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// Configure CFG1: baud rate and data size
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var cfg1 uint32
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// Set baud rate (MBR bits [30:28])
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cfg1 |= spi.getBaudRate(config)
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// Set data size to 8 bits (DSIZE[4:0] = 7 = 8-1)
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cfg1 |= 7
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spi.Bus.CFG1.Set(cfg1)
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// Configure CFG2: master mode, SS output, polarity, phase
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var cfg2 uint32
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const (
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cfg2_MASTER = 1 << 22 // MASTER bit
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cfg2_SSM = 1 << 26 // Software SS management
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cfg2_SSOE = 1 << 29 // SS output enable
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cfg2_AFCNTR = 1 << 31 // Alternate function GPIO control always active
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cfg2_CPOL = 1 << 25
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cfg2_CPHA = 1 << 24
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cfg2_LSBFRST = 1 << 23
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)
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cfg2 |= cfg2_MASTER | cfg2_SSM | cfg2_AFCNTR
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// Set polarity and phase
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switch config.Mode {
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case Mode1:
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cfg2 |= cfg2_CPHA
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case Mode2:
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cfg2 |= cfg2_CPOL
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case Mode3:
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cfg2 |= cfg2_CPOL | cfg2_CPHA
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}
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// Set bit transfer order
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if config.LSBFirst {
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cfg2 |= cfg2_LSBFRST
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}
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spi.Bus.CFG2.Set(cfg2)
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// Enable SPI
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spi.Bus.CR1.SetBits(1) // Set SPE (bit 0)
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return nil
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}
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// Transfer writes/reads a single byte using the SPI interface.
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func (spi *SPI) Transfer(w byte) (byte, error) {
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// Set transfer size to 1 frame
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spi.Bus.CR2.Set(1)
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// Start the transfer
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spi.Bus.CR1.SetBits(1 << 9) // CSTART bit
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// Wait until TX FIFO is ready (TXP bit in SR)
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const sr_TXP = 1 << 1
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const sr_RXP = 1 << 0
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const sr_EOT = 1 << 3
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for !spi.Bus.SR.HasBits(sr_TXP) {
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}
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// Write byte to TXDR
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spi.Bus.TXDR.Set(uint32(w))
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// Wait for RX data available (RXP bit in SR)
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for !spi.Bus.SR.HasBits(sr_RXP) {
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}
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// Read received byte
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data := byte(spi.Bus.RXDR.Get())
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// Wait for end of transfer
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for !spi.Bus.SR.HasBits(sr_EOT) {
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}
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// Clear EOT flag
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spi.Bus.IFCR.Set(sr_EOT)
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return data, nil
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}
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