mirror of
https://github.com/tinygo-org/tinygo.git
synced 2026-08-04 19:17:47 +00:00
Ayke van Laethem
1270a50104
The encoding/binary package in Go 1.23 imports the slices package, which results in circular import when imported from the machine package. Therefore, encoding/binary cannot be used in the machine package. This commit fixes that by introducing a new internal/binary package that is just plain Go code without dependencies. It can be safely used anywhere (including the runtime if needed).
937 lines
27 KiB
Go
937 lines
27 KiB
Go
//go:build stm32f4
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package machine
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// Peripheral abstraction layer for the stm32f4
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import (
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"device/stm32"
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"errors"
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"internal/binary"
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"math/bits"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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var deviceIDAddr = []uintptr{0x1FFF7A10, 0x1FFF7A14, 0x1FFF7A18}
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD4 = portD + 4
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PD5 = portD + 5
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PD6 = portD + 6
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PD7 = portD + 7
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PD8 = portD + 8
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PD9 = portD + 9
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PD10 = portD + 10
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PD11 = portD + 11
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PD12 = portD + 12
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PD13 = portD + 13
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PD14 = portD + 14
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PD15 = portD + 15
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PE0 = portE + 0
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PE1 = portE + 1
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PE2 = portE + 2
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PE7 = portE + 7
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PE8 = portE + 8
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PE9 = portE + 9
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PE10 = portE + 10
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PE11 = portE + 11
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PE12 = portE + 12
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PE13 = portE + 13
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PE14 = portE + 14
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PE15 = portE + 15
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PF0 = portF + 0
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PF1 = portF + 1
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PF2 = portF + 2
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PF3 = portF + 3
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PF4 = portF + 4
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PF5 = portF + 5
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PF6 = portF + 6
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PF7 = portF + 7
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PF8 = portF + 8
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PF9 = portF + 9
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PF10 = portF + 10
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PF11 = portF + 11
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PF12 = portF + 12
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PF13 = portF + 13
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PF14 = portF + 14
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PF15 = portF + 15
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PG0 = portG + 0
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PG1 = portG + 1
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PG2 = portG + 2
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PG3 = portG + 3
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PG4 = portG + 4
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PG5 = portG + 5
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PG6 = portG + 6
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PG7 = portG + 7
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PG8 = portG + 8
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PG9 = portG + 9
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PG10 = portG + 10
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PG11 = portG + 11
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PG12 = portG + 12
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PG13 = portG + 13
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PG14 = portG + 14
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PG15 = portG + 15
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PH0 = portH + 0
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PH1 = portH + 1
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PH2 = portH + 2
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PH3 = portH + 3
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PH4 = portH + 4
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PH5 = portH + 5
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PH6 = portH + 6
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PH7 = portH + 7
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PH8 = portH + 8
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PH9 = portH + 9
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PH10 = portH + 10
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PH11 = portH + 11
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PH12 = portH + 12
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PH13 = portH + 13
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PH14 = portH + 14
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PH15 = portH + 15
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PI0 = portI + 0
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PI1 = portI + 1
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PI2 = portI + 2
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PI3 = portI + 3
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PI4 = portI + 4
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PI5 = portI + 5
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PI6 = portI + 6
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PI7 = portI + 7
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PI8 = portI + 8
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PI9 = portI + 9
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PI10 = portI + 10
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PI11 = portI + 11
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PI12 = portI + 12
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PI13 = portI + 13
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PI14 = portI + 14
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PI15 = portI + 15
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PK0 = portK + 0
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PK1 = portK + 1
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PK2 = portK + 2
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PK3 = portK + 3
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PK4 = portK + 4
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PK5 = portK + 5
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PK6 = portK + 6
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PK7 = portK + 7
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PK8 = portK + 8
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PK9 = portK + 9
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PK10 = portK + 10
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PK11 = portK + 11
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PK12 = portK + 12
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PK13 = portK + 13
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PK14 = portK + 14
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PK15 = portK + 15
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 3:
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return stm32.GPIOD
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case 4:
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return stm32.GPIOE
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case 5:
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return stm32.GPIOF
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case 6:
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return stm32.GPIOG
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case 7:
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return stm32.GPIOH
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case 8:
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return stm32.GPIOI
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case 9:
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return stm32.GPIOJ
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case 10:
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return stm32.GPIOK
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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bit := p / 16
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if 0 <= bit && bit <= 10 {
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stm32.RCC.AHB1ENR.SetBits(0b1 << bit)
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} else {
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panic("machine: unknown port")
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}
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}
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func (p Pin) registerInterrupt() interrupt.Interrupt {
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pin := uint8(p) % 16
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switch pin {
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case 0:
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return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) })
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case 1:
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return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) })
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case 2:
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return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) })
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case 3:
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return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) })
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case 4:
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return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) })
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case 5:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) })
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case 6:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) })
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case 7:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) })
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case 8:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) })
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case 9:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) })
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case 10:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) })
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case 11:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) })
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case 12:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) })
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case 13:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) })
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case 14:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) })
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case 15:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) })
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}
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return interrupt.Interrupt{}
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}
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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case unsafe.Pointer(stm32.DAC): // DAC interface clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN)
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case unsafe.Pointer(stm32.PWR): // Power interface clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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case unsafe.Pointer(stm32.CAN2): // CAN 2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_CAN2EN)
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case unsafe.Pointer(stm32.CAN1): // CAN 1 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_CAN1EN)
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case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
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case unsafe.Pointer(stm32.UART5): // UART5 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART5EN)
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case unsafe.Pointer(stm32.UART4): // UART4 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART4EN)
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case unsafe.Pointer(stm32.USART3): // USART3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART3EN)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
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case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI3EN)
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case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN)
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case unsafe.Pointer(stm32.TIM14): // TIM14 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM14EN)
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case unsafe.Pointer(stm32.TIM13): // TIM13 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM13EN)
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case unsafe.Pointer(stm32.TIM12): // TIM12 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM12EN)
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case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
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case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN)
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case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM5EN)
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case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM4EN)
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case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN)
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case unsafe.Pointer(stm32.TIM11): // TIM11 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM11EN)
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case unsafe.Pointer(stm32.TIM10): // TIM10 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM10EN)
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case unsafe.Pointer(stm32.TIM9): // TIM9 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM9EN)
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case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
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case unsafe.Pointer(stm32.SDIO): // SDIO clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SDIOEN)
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case unsafe.Pointer(stm32.ADC3): // ADC3 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC3EN)
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case unsafe.Pointer(stm32.ADC2): // ADC2 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC2EN)
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case unsafe.Pointer(stm32.ADC1): // ADC1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN)
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case unsafe.Pointer(stm32.USART6): // USART6 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART6EN)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
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case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN)
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case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
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}
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}
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//---------- Timer related code
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var (
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TIM1 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM1EN,
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Device: stm32.TIM1,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA8, AF1_TIM1_2}, {PE9, AF1_TIM1_2}}},
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TimerChannel{Pins: []PinFunction{{PA9, AF1_TIM1_2}, {PE11, AF1_TIM1_2}}},
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TimerChannel{Pins: []PinFunction{{PA10, AF1_TIM1_2}, {PE13, AF1_TIM1_2}}},
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TimerChannel{Pins: []PinFunction{{PA11, AF1_TIM1_2}, {PE14, AF1_TIM1_2}}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM2EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA0, AF1_TIM1_2}, {PA5, AF1_TIM1_2}, {PA15, AF1_TIM1_2}}},
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TimerChannel{Pins: []PinFunction{{PA1, AF1_TIM1_2}, {PB3, AF1_TIM1_2}}},
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TimerChannel{Pins: []PinFunction{{PA2, AF1_TIM1_2}, {PB10, AF1_TIM1_2}}},
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TimerChannel{Pins: []PinFunction{{PA3, AF1_TIM1_2}, {PB11, AF1_TIM1_2}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM3 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM3EN,
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Device: stm32.TIM3,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA6, AF2_TIM3_4_5}, {PB4, AF2_TIM3_4_5}, {PC6, AF2_TIM3_4_5}}},
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TimerChannel{Pins: []PinFunction{{PA7, AF2_TIM3_4_5}, {PB5, AF2_TIM3_4_5}, {PC7, AF2_TIM3_4_5}}},
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TimerChannel{Pins: []PinFunction{{PB0, AF2_TIM3_4_5}, {PC8, AF2_TIM3_4_5}}},
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TimerChannel{Pins: []PinFunction{{PB1, AF2_TIM3_4_5}, {PC9, AF2_TIM3_4_5}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM4 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM4EN,
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Device: stm32.TIM4,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PB6, AF2_TIM3_4_5}, {PD12, AF2_TIM3_4_5}}},
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TimerChannel{Pins: []PinFunction{{PB7, AF2_TIM3_4_5}, {PD13, AF2_TIM3_4_5}}},
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TimerChannel{Pins: []PinFunction{{PB8, AF2_TIM3_4_5}, {PD14, AF2_TIM3_4_5}}},
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TimerChannel{Pins: []PinFunction{{PB9, AF2_TIM3_4_5}, {PD15, AF2_TIM3_4_5}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM5 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM5EN,
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Device: stm32.TIM5,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PH10, AF2_TIM3_4_5}}},
|
|
TimerChannel{Pins: []PinFunction{{PH11, AF2_TIM3_4_5}}},
|
|
TimerChannel{Pins: []PinFunction{{PH12, AF2_TIM3_4_5}}},
|
|
TimerChannel{Pins: []PinFunction{{PI0, AF2_TIM3_4_5}}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM6 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM6EN,
|
|
Device: stm32.TIM6,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM7 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM7EN,
|
|
Device: stm32.TIM7,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM8 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM8EN,
|
|
Device: stm32.TIM8,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PC6, AF3_TIM8_9_10_11}, {PI5, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{{PC7, AF3_TIM8_9_10_11}, {PI6, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{{PC8, AF3_TIM8_9_10_11}, {PI7, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{{PC9, AF3_TIM8_9_10_11}, {PI2, AF3_TIM8_9_10_11}}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM9 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM9EN,
|
|
Device: stm32.TIM9,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PA2, AF3_TIM8_9_10_11}, {PE5, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{{PA3, AF3_TIM8_9_10_11}, {PE6, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM10 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM10EN,
|
|
Device: stm32.TIM10,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PB8, AF3_TIM8_9_10_11}, {PF6, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM11 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM11EN,
|
|
Device: stm32.TIM11,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PB9, AF3_TIM8_9_10_11}, {PF7, AF3_TIM8_9_10_11}}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM12 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM12EN,
|
|
Device: stm32.TIM12,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PB14, AF9_CAN1_CAN2_TIM12_13_14}, {PH6, AF9_CAN1_CAN2_TIM12_13_14}}},
|
|
TimerChannel{Pins: []PinFunction{{PB15, AF9_CAN1_CAN2_TIM12_13_14}, {PH9, AF9_CAN1_CAN2_TIM12_13_14}}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM13 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM13EN,
|
|
Device: stm32.TIM13,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PA6, AF9_CAN1_CAN2_TIM12_13_14}, {PF8, AF9_CAN1_CAN2_TIM12_13_14}}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM14 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM14EN,
|
|
Device: stm32.TIM14,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{{PA7, AF9_CAN1_CAN2_TIM12_13_14}, {PF9, AF9_CAN1_CAN2_TIM12_13_14}}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
)
|
|
|
|
func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
|
|
switch t {
|
|
case &TIM1:
|
|
return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM1.handleUPInterrupt)
|
|
case &TIM2:
|
|
return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
|
|
case &TIM3:
|
|
return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt)
|
|
case &TIM4:
|
|
return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt)
|
|
case &TIM5:
|
|
return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt)
|
|
case &TIM6:
|
|
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
|
|
case &TIM7:
|
|
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
|
|
case &TIM8:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM8.handleUPInterrupt)
|
|
case &TIM9:
|
|
return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleUPInterrupt)
|
|
case &TIM10:
|
|
return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleUPInterrupt)
|
|
case &TIM11:
|
|
return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleUPInterrupt)
|
|
case &TIM12:
|
|
return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleUPInterrupt)
|
|
case &TIM13:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleUPInterrupt)
|
|
case &TIM14:
|
|
return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleUPInterrupt)
|
|
}
|
|
|
|
return interrupt.Interrupt{}
|
|
}
|
|
|
|
func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
|
|
switch t {
|
|
case &TIM1:
|
|
return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt)
|
|
case &TIM2:
|
|
return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
|
|
case &TIM3:
|
|
return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt)
|
|
case &TIM4:
|
|
return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt)
|
|
case &TIM5:
|
|
return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt)
|
|
case &TIM6:
|
|
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
|
|
case &TIM7:
|
|
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
|
|
case &TIM8:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM8.handleOCInterrupt)
|
|
case &TIM9:
|
|
return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleOCInterrupt)
|
|
case &TIM10:
|
|
return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleOCInterrupt)
|
|
case &TIM11:
|
|
return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleOCInterrupt)
|
|
case &TIM12:
|
|
return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleOCInterrupt)
|
|
case &TIM13:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleOCInterrupt)
|
|
case &TIM14:
|
|
return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleOCInterrupt)
|
|
}
|
|
|
|
return interrupt.Interrupt{}
|
|
}
|
|
|
|
func (t *TIM) enableMainOutput() {
|
|
t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE)
|
|
}
|
|
|
|
type arrtype = uint32
|
|
type arrRegType = volatile.Register32
|
|
|
|
const (
|
|
ARR_MAX = 0x10000
|
|
PSC_MAX = 0x10000
|
|
)
|
|
|
|
func initRNG() {
|
|
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_RNGEN)
|
|
stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN)
|
|
}
|
|
|
|
// Alternative peripheral pin functions
|
|
const (
|
|
AF0_SYSTEM = 0
|
|
AF1_TIM1_2 = 1
|
|
AF2_TIM3_4_5 = 2
|
|
AF3_TIM8_9_10_11 = 3
|
|
AF4_I2C1_2_3 = 4
|
|
AF5_SPI1_SPI2 = 5
|
|
AF6_SPI3 = 6
|
|
AF7_USART1_2_3 = 7
|
|
AF8_USART4_5_6 = 8
|
|
AF9_CAN1_CAN2_TIM12_13_14 = 9
|
|
AF10_OTG_FS_OTG_HS = 10
|
|
AF11_ETH = 11
|
|
AF12_FSMC_SDIO_OTG_HS_1 = 12
|
|
AF13_DCMI = 13
|
|
AF14 = 14
|
|
AF15_EVENTOUT = 15
|
|
)
|
|
|
|
// -- UART ---------------------------------------------------------------------
|
|
|
|
func (uart *UART) configurePins(config UARTConfig) {
|
|
// enable the alternate functions on the TX and RX pins
|
|
config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector)
|
|
config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector)
|
|
}
|
|
|
|
func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
|
|
var clock uint32
|
|
switch uart.Bus {
|
|
case stm32.USART1, stm32.USART6:
|
|
clock = CPUFrequency() / 2 // APB2 Frequency
|
|
case stm32.USART2, stm32.USART3, stm32.UART4, stm32.UART5:
|
|
clock = CPUFrequency() / 4 // APB1 Frequency
|
|
}
|
|
return clock / baudRate
|
|
}
|
|
|
|
func (uart *UART) setRegisters() {
|
|
uart.rxReg = &uart.Bus.DR
|
|
uart.txReg = &uart.Bus.DR
|
|
uart.statusReg = &uart.Bus.SR
|
|
uart.txEmptyFlag = stm32.USART_SR_TXE
|
|
}
|
|
|
|
// -- SPI ----------------------------------------------------------------------
|
|
|
|
type SPI struct {
|
|
Bus *stm32.SPI_Type
|
|
AltFuncSelector uint8
|
|
}
|
|
|
|
func (spi SPI) config8Bits() {
|
|
// no-op on this series
|
|
}
|
|
|
|
func (spi SPI) configurePins(config SPIConfig) {
|
|
config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector)
|
|
config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector)
|
|
config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector)
|
|
}
|
|
|
|
func (spi SPI) getBaudRate(config SPIConfig) uint32 {
|
|
var clock uint32
|
|
switch spi.Bus {
|
|
case stm32.SPI1:
|
|
clock = CPUFrequency() / 2
|
|
case stm32.SPI2, stm32.SPI3:
|
|
clock = CPUFrequency() / 4
|
|
}
|
|
|
|
// limit requested frequency to bus frequency and min frequency (DIV256)
|
|
freq := config.Frequency
|
|
if min := clock / 256; freq < min {
|
|
freq = min
|
|
} else if freq > clock {
|
|
freq = clock
|
|
}
|
|
|
|
// calculate the exact clock divisor (freq=clock/div -> div=clock/freq).
|
|
// truncation is fine, since it produces a less-than-or-equal divisor, and
|
|
// thus a greater-than-or-equal frequency.
|
|
// divisors only come in consecutive powers of 2, so we can use log2 (or,
|
|
// equivalently, bits.Len - 1) to convert to respective enum value.
|
|
div := bits.Len32(clock/freq) - 1
|
|
|
|
// but DIV1 (2^0) is not permitted, as the least divisor is DIV2 (2^1), so
|
|
// subtract 1 from the log2 value, keeping a lower bound of 0
|
|
if div < 0 {
|
|
div = 0
|
|
} else if div > 0 {
|
|
div--
|
|
}
|
|
|
|
// finally, shift the enumerated value into position for SPI CR1
|
|
return uint32(div) << stm32.SPI_CR1_BR_Pos
|
|
}
|
|
|
|
// -- I2C ----------------------------------------------------------------------
|
|
|
|
type I2C struct {
|
|
Bus *stm32.I2C_Type
|
|
AltFuncSelector uint8
|
|
}
|
|
|
|
func (i2c *I2C) configurePins(config I2CConfig) {
|
|
config.SCL.ConfigureAltFunc(PinConfig{Mode: PinModeI2CSCL}, i2c.AltFuncSelector)
|
|
config.SDA.ConfigureAltFunc(PinConfig{Mode: PinModeI2CSDA}, i2c.AltFuncSelector)
|
|
}
|
|
|
|
func (i2c *I2C) getFreqRange(config I2CConfig) uint32 {
|
|
// all I2C interfaces are on APB1
|
|
clock := CPUFrequency() / 4
|
|
// convert to MHz
|
|
clock /= 1000000
|
|
// must be between 2 MHz (or 4 MHz for fast mode (Fm)) and 50 MHz, inclusive
|
|
var min, max uint32 = 2, 50
|
|
if config.Frequency > 100000 {
|
|
min = 4 // fast mode (Fm)
|
|
}
|
|
if clock < min {
|
|
clock = min
|
|
} else if clock > max {
|
|
clock = max
|
|
}
|
|
return clock << stm32.I2C_CR2_FREQ_Pos
|
|
}
|
|
|
|
func (i2c *I2C) getRiseTime(config I2CConfig) uint32 {
|
|
// These bits must be programmed with the maximum SCL rise time given in the
|
|
// I2C bus specification, incremented by 1.
|
|
// For instance: in Sm mode, the maximum allowed SCL rise time is 1000 ns.
|
|
// If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08
|
|
// and PCLK1 = 125 ns, therefore the TRISE[5:0] bits must be programmed with
|
|
// 09h (1000 ns / 125 ns = 8 + 1)
|
|
freqRange := i2c.getFreqRange(config)
|
|
if config.Frequency > 100000 {
|
|
// fast mode (Fm) adjustment
|
|
freqRange *= 300
|
|
freqRange /= 1000
|
|
}
|
|
return (freqRange + 1) << stm32.I2C_TRISE_TRISE_Pos
|
|
}
|
|
|
|
func (i2c *I2C) getSpeed(config I2CConfig) uint32 {
|
|
ccr := func(pclk uint32, freq uint32, coeff uint32) uint32 {
|
|
return (((pclk - 1) / (freq * coeff)) + 1) & stm32.I2C_CCR_CCR_Msk
|
|
}
|
|
sm := func(pclk uint32, freq uint32) uint32 { // standard mode (Sm)
|
|
if s := ccr(pclk, freq, 2); s < 4 {
|
|
return 4
|
|
} else {
|
|
return s
|
|
}
|
|
}
|
|
fm := func(pclk uint32, freq uint32, duty uint8) uint32 { // fast mode (Fm)
|
|
if duty == DutyCycle2 {
|
|
return ccr(pclk, freq, 3)
|
|
} else {
|
|
return ccr(pclk, freq, 25) | stm32.I2C_CCR_DUTY
|
|
}
|
|
}
|
|
// all I2C interfaces are on APB1
|
|
clock := CPUFrequency() / 4
|
|
if config.Frequency <= 100000 {
|
|
return sm(clock, config.Frequency)
|
|
} else {
|
|
s := fm(clock, config.Frequency, config.DutyCycle)
|
|
if (s & stm32.I2C_CCR_CCR_Msk) == 0 {
|
|
return 1
|
|
} else {
|
|
return s | stm32.I2C_CCR_F_S
|
|
}
|
|
}
|
|
}
|
|
|
|
//---------- Flash related code
|
|
|
|
// the block size actually depends on the sector.
|
|
// TODO: handle this correctly for sectors > 3
|
|
const eraseBlockSizeValue = 16384
|
|
|
|
// see RM0090 page 75
|
|
func sectorNumber(address uintptr) uint32 {
|
|
switch {
|
|
// 0x0800 0000 - 0x0800 3FFF
|
|
case address >= 0x08000000 && address <= 0x08003FFF:
|
|
return 0
|
|
// 0x0800 4000 - 0x0800 7FFF
|
|
case address >= 0x08004000 && address <= 0x08007FFF:
|
|
return 1
|
|
// 0x0800 8000 - 0x0800 BFFF
|
|
case address >= 0x08008000 && address <= 0x0800BFFF:
|
|
return 2
|
|
// 0x0800 C000 - 0x0800 FFFF
|
|
case address >= 0x0800C000 && address <= 0x0800FFFF:
|
|
return 3
|
|
// 0x0801 0000 - 0x0801 FFFF
|
|
case address >= 0x08010000 && address <= 0x0801FFFF:
|
|
return 4
|
|
// 0x0802 0000 - 0x0803 FFFF
|
|
case address >= 0x08020000 && address <= 0x0803FFFF:
|
|
return 5
|
|
// 0x0804 0000 - 0x0805 FFFF
|
|
case address >= 0x08040000 && address <= 0x0805FFFF:
|
|
return 6
|
|
case address >= 0x08060000 && address <= 0x0807FFFF:
|
|
return 7
|
|
case address >= 0x08080000 && address <= 0x0809FFFF:
|
|
return 8
|
|
case address >= 0x080A0000 && address <= 0x080BFFFF:
|
|
return 9
|
|
case address >= 0x080C0000 && address <= 0x080DFFFF:
|
|
return 10
|
|
case address >= 0x080E0000 && address <= 0x080FFFFF:
|
|
return 11
|
|
default:
|
|
return 0
|
|
}
|
|
}
|
|
|
|
// calculate sector number from address
|
|
// var sector uint32 = sectorNumber(address)
|
|
|
|
// see RM0090 page 85
|
|
// eraseBlock at the passed in block number
|
|
func eraseBlock(block uint32) error {
|
|
waitUntilFlashDone()
|
|
|
|
// clear any previous errors
|
|
stm32.FLASH.SR.SetBits(0xF0)
|
|
|
|
// set SER bit
|
|
stm32.FLASH.SetCR_SER(1)
|
|
defer stm32.FLASH.SetCR_SER(0)
|
|
|
|
// set the block (aka sector) to be erased
|
|
stm32.FLASH.SetCR_SNB(block)
|
|
defer stm32.FLASH.SetCR_SNB(0)
|
|
|
|
// start the page erase
|
|
stm32.FLASH.SetCR_STRT(1)
|
|
|
|
waitUntilFlashDone()
|
|
|
|
if err := checkError(); err != nil {
|
|
return err
|
|
}
|
|
|
|
return nil
|
|
}
|
|
|
|
const writeBlockSize = 2
|
|
|
|
// see RM0090 page 86
|
|
// must write data in word-length
|
|
func writeFlashData(address uintptr, data []byte) (int, error) {
|
|
if len(data)%writeBlockSize != 0 {
|
|
return 0, errFlashInvalidWriteLength
|
|
}
|
|
|
|
waitUntilFlashDone()
|
|
|
|
// clear any previous errors
|
|
stm32.FLASH.SR.SetBits(0xF0)
|
|
|
|
// set parallelism to x32
|
|
stm32.FLASH.SetCR_PSIZE(2)
|
|
|
|
for i := 0; i < len(data); i += writeBlockSize {
|
|
// start write operation
|
|
stm32.FLASH.SetCR_PG(1)
|
|
|
|
*(*uint16)(unsafe.Pointer(address)) = binary.LittleEndian.Uint16(data[i : i+writeBlockSize])
|
|
|
|
waitUntilFlashDone()
|
|
|
|
if err := checkError(); err != nil {
|
|
return i, err
|
|
}
|
|
|
|
// end write operation
|
|
stm32.FLASH.SetCR_PG(0)
|
|
}
|
|
|
|
return len(data), nil
|
|
}
|
|
|
|
func waitUntilFlashDone() {
|
|
for stm32.FLASH.GetSR_BSY() != 0 {
|
|
}
|
|
}
|
|
|
|
var (
|
|
errFlashPGS = errors.New("errFlashPGS")
|
|
errFlashPGP = errors.New("errFlashPGP")
|
|
errFlashPGA = errors.New("errFlashPGA")
|
|
errFlashWRP = errors.New("errFlashWRP")
|
|
)
|
|
|
|
func checkError() error {
|
|
switch {
|
|
case stm32.FLASH.GetSR_PGSERR() != 0:
|
|
return errFlashPGS
|
|
case stm32.FLASH.GetSR_PGPERR() != 0:
|
|
return errFlashPGP
|
|
case stm32.FLASH.GetSR_PGAERR() != 0:
|
|
return errFlashPGA
|
|
case stm32.FLASH.GetSR_WRPERR() != 0:
|
|
return errFlashWRP
|
|
}
|
|
|
|
return nil
|
|
}
|