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5557e97888
This updates lib/cmsis-svd, pulling in the updates to the Espressif SVD files here: https://github.com/cmsis-svd/cmsis-svd-data/pull/3 This is needed for wifi/BLE support on the ESP32-C3 (the older SVD files were missing some necessary interrupts).
102 lines
3.0 KiB
Go
102 lines
3.0 KiB
Go
//go:build esp32c3
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package runtime
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import (
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"device/esp"
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"device/riscv"
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"machine"
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"runtime/volatile"
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"unsafe"
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)
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// This is the function called on startup after the flash (IROM/DROM) is
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// initialized and the stack pointer has been set.
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//
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//export main
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func main() {
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// This initialization configures the following things:
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// * It disables all watchdog timers. They might be useful at some point in
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// the future, but will need integration into the scheduler. For now,
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// they're all disabled.
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// * It sets the CPU frequency to 160MHz, which is the maximum speed allowed
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// for this CPU. Lower frequencies might be possible in the future, but
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// running fast and sleeping quickly is often also a good strategy to save
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// power.
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// TODO: protect certain memory regions, especially the area below the stack
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// to protect against stack overflows. See
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// esp_cpu_configure_region_protection in ESP-IDF.
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// Disable Timer 0 watchdog.
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esp.TIMG0.WDTCONFIG0.Set(0)
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// Disable RTC watchdog.
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esp.RTC_CNTL.WDTWPROTECT.Set(0x50D83AA1)
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esp.RTC_CNTL.WDTCONFIG0.Set(0)
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// Disable super watchdog.
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esp.RTC_CNTL.SWD_WPROTECT.Set(0x8F1D312A)
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esp.RTC_CNTL.SWD_CONF.Set(esp.RTC_CNTL_SWD_CONF_SWD_DISABLE)
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// Change CPU frequency from 20MHz to 80MHz, by switching from the XTAL to
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// the PLL clock source (see table "CPU Clock Frequency" in the reference
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// manual).
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esp.SYSTEM.SYSCLK_CONF.Set(1 << esp.SYSTEM_SYSCLK_CONF_SOC_CLK_SEL_Pos)
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// Change CPU frequency from 80MHz to 160MHz by setting SYSTEM_CPUPERIOD_SEL
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// to 1 (see table "CPU Clock Frequency" in the reference manual).
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// Note: we might not want to set SYSTEM_CPU_WAIT_MODE_FORCE_ON to save
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// power. It is set here to keep the default on reset.
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esp.SYSTEM.CPU_PER_CONF.Set(esp.SYSTEM_CPU_PER_CONF_CPU_WAIT_MODE_FORCE_ON | esp.SYSTEM_CPU_PER_CONF_PLL_FREQ_SEL | 1<<esp.SYSTEM_CPU_PER_CONF_CPUPERIOD_SEL_Pos)
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clearbss()
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// Configure interrupt handler
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interruptInit()
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// Initialize UART.
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machine.USBCDC.Configure(machine.UARTConfig{})
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machine.InitSerial()
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// Initialize main system timer used for time.Now.
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initTimer()
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// Initialize the heap, call main.main, etc.
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run()
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// Fallback: if main ever returns, hang the CPU.
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exit(0)
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}
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func abort() {
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// lock up forever
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for {
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riscv.Asm("wfi")
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}
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}
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// interruptInit initialize the interrupt controller and called from runtime once.
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func interruptInit() {
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mie := riscv.DisableInterrupts()
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// Reset all interrupt source priorities to zero.
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priReg := &esp.INTERRUPT_CORE0.CPU_INT_PRI_1
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for i := 0; i < 31; i++ {
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priReg.Set(0)
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priReg = (*volatile.Register32)(unsafe.Add(unsafe.Pointer(priReg), 4))
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}
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// default threshold for interrupts is 5
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esp.INTERRUPT_CORE0.CPU_INT_THRESH.Set(5)
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// Set the interrupt address.
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// Set MODE field to 1 - a vector base address (only supported by ESP32C3)
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// Note that this address must be aligned to 256 bytes.
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riscv.MTVEC.Set((uintptr(unsafe.Pointer(&_vector_table))) | 1)
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riscv.EnableInterrupts(mie)
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}
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//go:extern _vector_table
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var _vector_table [0]uintptr
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