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https://github.com/tinygo-org/tinygo.git
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Konstantin Sharlaimov
5f02d6b659
Define the board's external crystal (HSE) frequency `xtalHz` in the respective `board_*.go` files. Per-topology PLL tables (F1, F4, F7) will compute the register dividers from it. Moving this parameter to the board definition level cleanly isolates board hardware characteristics from general MCU chip configurations, eliminating the need for custom target build tags. Targets using HSE-clocked STM32 chips must define `xtalHz` or fail to build.
69 lines
1.9 KiB
Go
69 lines
1.9 KiB
Go
//go:build stm32 && stm32f103
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package runtime
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import (
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"device/stm32"
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"machine"
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)
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func init() {
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initCLK()
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machine.InitSerial()
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initTickTimer(&machine.TIM4)
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}
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func putchar(c byte) {
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machine.Serial.WriteByte(c)
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}
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func getchar() byte {
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for machine.Serial.Buffered() == 0 {
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Gosched()
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}
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v, _ := machine.Serial.ReadByte()
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return v
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}
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func buffered() int {
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return machine.Serial.Buffered()
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}
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// initCLK sets clock to 72MHz using the board's HSE crystal (defined by the xtalHz) w/ PLL.
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func initCLK() {
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pll := machine.PLLParams72MHz()
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stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2) // Two wait states, per datasheet
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_ADCPRE_Div6 << stm32.RCC_CFGR_ADCPRE_Pos) // prescale ADCCLK = PCLK2/6
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON) // enable HSE clock
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// wait for the HSEREADY flag
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
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}
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION) // enable HSI clock
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// wait for the HSIREADY flag
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) {
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}
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PLLSRC) // set PLL source to HSE
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stm32.RCC.CFGR.SetBits(pll.Prediv << stm32.RCC_CFGR_PLLXTPRE_Pos) // optional HSE /2 prescaler
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stm32.RCC.CFGR.SetBits(pll.Mul << stm32.RCC_CFGR_PLLMUL_Pos) // PLL multiplier
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON) // enable the PLL
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// wait for the PLLRDY flag
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
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}
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_SW_PLL) // set clock source to pll
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// wait for PLL to be CLK
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for !stm32.RCC.CFGR.HasBits(stm32.RCC_CFGR_SWS_PLL << stm32.RCC_CFGR_SWS_Pos) {
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}
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}
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