- Uses PLL1 to boost the system clock from the 4 MHz MSIS default to 160 MHz.
- Sets VOS to Range 1 (1.2V) and enables the EPOD booster for higher frequency support.
- Configures flash latency (4 wait states) and enables prefetch for 160 MHz operation.
- Updates CPU and APB timer frequencies in the machine package accordingly.
- Fixes LPUART baud rate divisor computation by using 64-bit arithmetic to prevent
overflow with the newly increased 160 MHz clock.
Signed-off-by: deadprogram <ron@hybridgroup.com>
This fixes several issues in the STM32 UART implementation:
- `writeByte` now waits for the transmit register to be empty before writing, preventing data loss by avoiding overwriting the shift register.
- `flush` now correctly waits for the Transmission Complete (TC) flag.
- The interrupt handler now clears all error flags (ORE, NE, FE, PE) to prevent interrupt storms, rather than just ORE.
- Extracted `SetBaudRate` so it can be cleanly overridden by specific MCU families.
It also introduces specific fixes for the STM32U5 family:
- Enforces a minimum BRR divisor of 16 in `getBaudRateDivisor` to prevent undefined hardware behavior and CPU starvation.
- Overrides `SetBaudRate` for STM32U585 to momentarily disable the USART (UE=0) before updating the BRR register, which is read-only when enabled.
- Adds a readback after enabling the USART1 clock to ensure the clock is active before register access.
Signed-off-by: deadprogram <ron@hybridgroup.com>
The UART handleInterrupt handler unconditionally read RDR on every
interrupt without checking which flag triggered it. On newer STM32
USART peripherals (U5, L4, L5, L0, G0, F7, WL), RXNEIE enables
interrupts for both RXFNE (data ready) and ORE (overrun error).
Unlike older families (F1, F4), ORE is not cleared by reading the
data register, it must be explicitly cleared via the ICR register.
When an overrun occurred (e.g. serial data arriving while ADC
busy-waits in Get()), ORE would trigger the interrupt, the handler
would fire without clearing it, and the interrupt would re-trigger
immediately, causing an infinite interrupt storm that locks up the
CPU.
Fix by:
- Checking RXFNE/RXNE (bit 5) before reading data from RDR
- Clearing ORE (bit 3) via ICR on newer peripherals when set
- Adding errClearReg field to UART struct, set to &Bus.ICR in
setRegisters() for all ICR-capable families
- Preserving the SR+DR clearing sequence for older F1/F4 families
Signed-off-by: deadprogram <ron@hybridgroup.com>
Signed-off-by: deadprogram <ron@hybridgroup.com>
machine/stm32u585: fix PWR peripheral clock was never enabled
On STM32U5, PWR is on AHB3 and requires RCC.AHB3ENR.PWREN -
unlike some other STM32 families where PWR is always clocked.
Without this, all writes to PWR registers (including IO2SV for
VDDIO2) were silently dropped, so GPIOG pins could never drive.
Signed-off-by: deadprogram <ron@hybridgroup.com>
target: correct I2C pin mapping for Arduino UNO Q
Signed-off-by: deadprogram <ron@hybridgroup.com>
The complex 160MHz PLL initialization was hanging the MCU.
The fix: Replaced the entire PLL-based clock init with the MSI 4MHz default
Signed-off-by: deadprogram <ron@hybridgroup.com>
Add SPIv2 driver for STM32U5 using TXDR/RXDR and CFG1/CFG2 registers,
which differ from the classic SPI peripheral on older STM32 families.
Implements Configure() and single-byte Transfer().
Add SPI1 peripheral and pin definitions to arduino-uno-q board.
Exclude stm32u5 from the shared classic SPI build tag.
Add I2C timing values for STM32U585 at 160MHz PCLK1 (10/100/400/500 KHz).
Add I2C1 peripheral and pin definitions to arduino-uno-q board.
Update i2c_revb build tag to include stm32u5.
Add machine-level support for STM32U5 family: GPIO ports A-I with clock
enables via AHB2ENR1, EXTI pin interrupts (individual EXTI0-15 IRQs),
timer definitions (TIM1-8, TIM15-17), RNG, and alternate function clock
enables for all peripherals.
Add UART support with STM32U585 baud rate and register configuration.
Add arduino-uno-q board pin definitions and USART2 serial.
Update shared build tags: gpio_revb, gpio_reva, exti_exti, exti_syscfg.
deadprogram