all: add HiFive1 rev B board with RISC-V architecture

This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
This commit is contained in:
Ayke van Laethem
2019-03-30 12:54:36 +01:00
committed by Ron Evans
parent f0eb4eef5a
commit ffa38b183b
37 changed files with 485 additions and 74 deletions
+19
View File
@@ -0,0 +1,19 @@
// +build tinygo.riscv
package runtime
import "device/riscv"
const GOARCH = "arm" // riscv pretends to be arm
// The bitness of the CPU (e.g. 8, 32, 64).
const TargetBits = 32
// Align on word boundary.
func align(ptr uintptr) uintptr {
return (ptr + 3) &^ 3
}
func getCurrentStackPointer() uintptr {
return riscv.ReadRegister("sp")
}